Intel ESM-2740 用户手册
ESM-2740/2743
34 ESM-2740/2743 User’s Manual
2.4.5
Signal Description – ETX Connector X2 (ETXB)
2.4.5.1 ISA
Signals
Signal
Signal Description
SD[0:15]
These signals provide data bus bits 0 to 15 for any peripheral devices. All 8-bit
devices use SD[0:7] for data transfers. 16-bit devices use SD[0:15].
To support 8-bit devices, the data on SD[8:15] is gated to SD[0:7] during 8-bit
transfers to these devices. 16-bit CPU cycles will be automatically converted into
two 8-bit cycles for 8-bit peripherals.
devices use SD[0:7] for data transfers. 16-bit devices use SD[0:15].
To support 8-bit devices, the data on SD[8:15] is gated to SD[0:7] during 8-bit
transfers to these devices. 16-bit CPU cycles will be automatically converted into
two 8-bit cycles for 8-bit peripherals.
SA[0:19]
Address bits 0 through 15 are used to address I/O devices. Address bits 0 through
19 are used to address memory within the system. These 20 address lines, in
addition to LA[17:23] allow access of up to 16MB of memory. SA[0:19] are gated
on the ISA-bus when BALE is high and latched on to the falling edge of BALE.
19 are used to address memory within the system. These 20 address lines, in
addition to LA[17:23] allow access of up to 16MB of memory. SA[0:19] are gated
on the ISA-bus when BALE is high and latched on to the falling edge of BALE.
SBHE#
Bus High Enable indicates a data transfer on the upper byte of the data bus
SD[8:15]. 16-bit I/O devices use SBHE# to enable data bus buffers on SD[8:15].
SD[8:15]. 16-bit I/O devices use SBHE# to enable data bus buffers on SD[8:15].
BALE
BALE is an active-high pulse generated at the beginning of any bus cycle initiated
by a CPU module. It indicates when the SA[0:19], LA17.23, AEN, and SBHE#
signals are valid.
by a CPU module. It indicates when the SA[0:19], LA17.23, AEN, and SBHE#
signals are valid.
AEN
AEN is an active-high output that indicates a DMA transfer cycle. Only resources
with a active DACK# signal should respond to the command lines when AEN is
high.
with a active DACK# signal should respond to the command lines when AEN is
high.
MEMR#
MEMR# instructs memory devices to drive data onto the data bus. MEMR# is
active for all memory read cycles.
active for all memory read cycles.
SMEMR#
SMEMR# instructs memory devices to drive data onto the data bus. SMEMR# is
active for memory read cycles to addresses below 1MB.
active for memory read cycles to addresses below 1MB.
MEMW#
MEMW# instructs memory devices to store the data present on the data bus.
MEMW# is active for all memory write cycles.
MEMW# is active for all memory write cycles.
SMEMW#
SMEMW# instructs memory devices to store the data present on the data bus.
SMEMW# is active for all memory write cycles to address below 1MB.
SMEMW# is active for all memory write cycles to address below 1MB.
IOR#
I/O read instructs an I/O device to drive its data onto the data bus. It may be driven
by the CPU or by the DMA controller. IOR# is inactive (high) during refresh cycles.
by the CPU or by the DMA controller. IOR# is inactive (high) during refresh cycles.
IOW#
I/O write instructs an I/O device to store the data present on the data bus. It may be
driven by the CPU or by the DMA controller. IOW# is inactive (high) during refresh
cycles.
driven by the CPU or by the DMA controller. IOW# is inactive (high) during refresh
cycles.
IOCHK#
IOCHK# is an active-low input signal that indicates that an error has occurred on
the module bus. If I/O checking is enabled on the CPU module, an IOCHK#
assertion by a peripheral device sends a NMI to the processor.
the module bus. If I/O checking is enabled on the CPU module, an IOCHK#
assertion by a peripheral device sends a NMI to the processor.
IOCHRDY
The I/O Channel Ready is pulled low in order to extend the read or write cycles of
any bus access when required. The CPU, DMA controllers or refresh controller can
initiate the cycle.
Any peripheral that cannot present read data or strobe in write data within this
amount of time use IOCHRDY to extend these cycles.
This signal should not be held low for more than 2.5 μs for normal operation. Any
extension to more than 2.5 μs does not guarantee proper DRAM memory content
due to the fact that memory refresh is disabled while IOCHRDY is low.
any bus access when required. The CPU, DMA controllers or refresh controller can
initiate the cycle.
Any peripheral that cannot present read data or strobe in write data within this
amount of time use IOCHRDY to extend these cycles.
This signal should not be held low for more than 2.5 μs for normal operation. Any
extension to more than 2.5 μs does not guarantee proper DRAM memory content
due to the fact that memory refresh is disabled while IOCHRDY is low.
M16#
The M16# signal determines when a 16-bit to 8-bit conversion is needed for
memory bus cycles. A conversion is done any time the CPU module requests a
16-bit memory cycle while the M16# line is high. If M16# is high, 16-bit CPU cycles
are automatically converted on the bus into two 8-bit cycles. If M16# is low, an
access to peripherals is done 16 bits wide.
memory bus cycles. A conversion is done any time the CPU module requests a
16-bit memory cycle while the M16# line is high. If M16# is high, 16-bit CPU cycles
are automatically converted on the bus into two 8-bit cycles. If M16# is low, an
access to peripherals is done 16 bits wide.
IO16#
The IO16# signal determines when a 16-bit to 8-bit conversion is needed for I/O
bus cycles. A conversion is done any time the CPU module requests a 16-bit I/O
cycle while the IO16# line is high. If IO16# is high, 16-bit CPU cycles are
automatically converted on the bus into two 8-bit cycles. If IO16# is low, an access
to peripherals is done at 16 bit width.
bus cycles. A conversion is done any time the CPU module requests a 16-bit I/O
cycle while the IO16# line is high. If IO16# is high, 16-bit CPU cycles are
automatically converted on the bus into two 8-bit cycles. If IO16# is low, an access
to peripherals is done at 16 bit width.