Intel 253668-032US 用户手册
Vol. 3 2-11
SYSTEM ARCHITECTURE OVERVIEW
running program or task. SMM-specific code may then be executed transparently.
Upon returning from SMM, the processor is placed back into its state prior to the
SMI.
Upon returning from SMM, the processor is placed back into its state prior to the
SMI.
•
Virtual-8086 mode — In protected mode, the processor supports a quasi-
operating mode known as virtual-8086 mode. This mode allows the processor
execute 8086 software in a protected, multitasking environment.
operating mode known as virtual-8086 mode. This mode allows the processor
execute 8086 software in a protected, multitasking environment.
Intel 64 architecture supports all operating modes of IA-32 architecture and IA-32e
modes:
modes:
•
IA-32e mode — In IA-32e mode, the processor supports two sub-modes:
compatibility mode and 64-bit mode. 64-bit mode provides 64-bit linear
addressing and support for physical address space larger than 64 GBytes.
Compatibility mode allows most legacy protected-mode applications to run
unchanged.
compatibility mode and 64-bit mode. 64-bit mode provides 64-bit linear
addressing and support for physical address space larger than 64 GBytes.
Compatibility mode allows most legacy protected-mode applications to run
unchanged.
Figure 2-3 shows how the processor moves between operating modes.
The processor is placed in real-address mode following power-up or a reset. The PE
flag in control register CR0 then controls whether the processor is operating in real-
address or protected mode. See also: Section 9.9, “Mode Switching.” and Section
4.1.2, “Paging-Mode Enabling.”
flag in control register CR0 then controls whether the processor is operating in real-
address or protected mode. See also: Section 9.9, “Mode Switching.” and Section
4.1.2, “Paging-Mode Enabling.”
Figure 2-3. Transitions Among the Processor’s Operating Modes
Real-Address
Protected Mode
Virtual-8086
Mode
System
Management
Mode
PE=1
Reset or
VM=1
VM=0
PE=0
Reset
or
RSM
SMI#
RSM
SMI#
RSM
SMI#
Reset
Mode
IA-32e
Mode
RSM
SMI#
LME=1, CR0.PG=1*
See**
* See Section 9.8.5
** See Section 9.8.5.4