Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 数据表
![Intel](https://files.manualsbrain.com/attachments/5a71b1e7f60391972dadeef20435931cbf4621a5/common/fit/150/50/86c99b5f14aeb2708e9a9e1b5305af4ccf882c1af0155dad25413c2ed84e/brand_logo.png)
产品代码
P4X-UPE3210-316-6M1333
Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel
®
3210 MCH only)
222
Datasheet
8.12
IOBASE1—I/O Base Address
B/D/F/Type:
0/6/0/PCI
Address Offset: 1Ch
Default Value:
F0h
Access:
RO, RW
Size:
8 bits
This register controls the processor to PCI Express I/O access routing based on the
following formula:
IO_BASE ≤ address ≤ IO_LIMIT
Only upper 4 bits are programmable. For the purpose of address decode address bits
A[11:0] are treated as 0. Thus the bottom of the defined I/O address range will be
aligned to a 4 KB boundary.
8.13
IOLIMIT1—I/O Limit Address
B/D/F/Type:
0/6/0/PCI
Address Offset: 1Dh
Default Value:
00h
Access:
RW, RO
Size:
8 bits
This register controls the processor to PCI Express I/O access routing based on the
following formula:
IO_BASE ≤ address ≤ IO_LIMIT
Only upper 4 bits are programmable. For the purpose of address decode address bits
A[11:0] are assumed to be FFFh. Thus, the top of the defined I/O address range will be
at the top of a 4 KB aligned address block.
Bit
Access
Default
Value
Description
7:4
RW
Fh
I/O Address Base (IOBASE): This field corresponds to A[15:12] of the I/O
addresses passed by bridge 1 to PCI Express.
addresses passed by bridge 1 to PCI Express.
3:0
RO
0h
Reserved
Bit
Access
Default
Value
Description
7:4
RW
0h
I/O Address Limit (IOLIMIT): Corresponds to A[15:12] of the I/O address
limit of device #6. Devices between this upper limit and IOBASE1 will be passed
to the PCI Express hierarchy associated with this device.
limit of device #6. Devices between this upper limit and IOBASE1 will be passed
to the PCI Express hierarchy associated with this device.
3:0
RO
0h
Reserved