Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 数据表

产品代码
P4X-UPE3210-316-6M1333
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页码 326
Host-Secondary PCI Express* Bridge Registers (D6:F0)  (Intel
®
 3210 MCH only)
230
Datasheet
8.21
CAPPTR1—Capabilities Pointer
B/D/F/Type:
0/6/0/PCI
Address Offset: 34h
Default Value:
88h
Access:
RO 
Size:
8 bits
The capabilities pointer provides the address offset to the location of the first entry in 
this device's linked list of capabilities.
8.22
INTRLINE1—Interrupt Line
B/D/F/Type:
0/6/0/PCI
Address Offset: 3Ch
Default Value:
00h
Access:
RW 
Size:
8 bits
This register contains interrupt line routing information. The device itself does not use 
this value, rather it is used by device drivers and operating systems to determine 
priority and vector information.
8.23
INTRPIN1—Interrupt Pin
B/D/F/Type:
0/6/0/PCI
Address Offset: 3Dh
Default Value:
01h
Access:
RO 
Size:
8 bits
This register specifies which interrupt pin this device uses.
Bit
Access
Default 
Value
Description
7:0
RO
88h
First Capability (CAPPTR1): The first capability in the list is the Subsystem ID 
and Subsystem Vendor ID Capability. 
Bit
Access
Default 
Value
Description
7:0
RW
00h
Interrupt Connection (INTCON): Used to communicate interrupt line routing 
information. 
Bit
Access
Default 
Value
Description
7:0
RO
01h
Interrupt Pin (INTPIN): As a single function device, the PCI Express device 
specifies INTA as its interrupt pin. 01h=INTA.