jetway 939gt4slir311 用户手册

  
 
 
                                                                                                                                                                                                                                                                                                                                                

 
 
 

 

The default setting is “Auto” for this selection, and it provides with the adjustable bandwidth 
selection for you to choose the combination of stream with x16 and x8 bandwidth of updoad 
and down between the processor and system chip. 

DRAM Timing Settings 
Please refer to section 3-6-1 

System BIOS Cacheable 
Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh, resulting in 
better system performance.  However, if any program writes to this memory area, a system 
error may result.  The settings are: Enabled and Disabled. 

↑↓→←

SDRAM RAS-to-CAS Delay 
This field let’s you insert a timing delay between the CAS and RAS strobe signals, used when 
DRAM is written to, read from, or refreshed.  Fast gives faster performance; and Slow gives 
more stable performance.  This field applies only when synchronous DRAM is installed in the 
system.  The settings are: 4T and 3T. 

SDRAM  Precharge Time 
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before 
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date.  Fast 
gives faster performance; and Slow gives more stable performance.  This field applies only 
when synchronous DRAM is installed in the system.  The settings are: 2T and 3T. 

DRAM CAS Latency 
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends 
on the DRAM timing.  The settings are: 2T and 2.5T.