Toshiba Xeon 2.8GHz UPG3843W 用户手册
产品代码
UPG3843W
Intel® Xeon™ Processor with 512 KB L2 Cache
12
Datasheet
The Intel
Xeon processor with 512 KB L2 cache uses a scalable front side bus protocol referred to
as the “front side bus” in this document. The processor front side bus utilizes a split-transaction,
deferred reply protocol similar to that introduced by the Pentium
deferred reply protocol similar to that introduced by the Pentium
®
Pro processor front side bus, but
is not compatible with the Pentium Pro processor front side bus. The Intel
Xeon processor with
512 KB L2 cache front side bus is compatible with the Intel Xeon processor front side bus. The
front side bus uses Source-Synchronous Transfer (SST) of address and data to improve
performance, and transfers data four times per bus clock (4X data transfer rate). Along with the 4X
data bus, the address bus can deliver addresses two times per bus clock and is referred to as a
‘double-clocked’ or 2X address bus. In addition, the Request Phase completes in one clock cycle.
Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 3.2
Gigabytes per second. Finally, the front side bus also introduces transactions that are used to
deliver interrupts.
front side bus uses Source-Synchronous Transfer (SST) of address and data to improve
performance, and transfers data four times per bus clock (4X data transfer rate). Along with the 4X
data bus, the address bus can deliver addresses two times per bus clock and is referred to as a
‘double-clocked’ or 2X address bus. In addition, the Request Phase completes in one clock cycle.
Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 3.2
Gigabytes per second. Finally, the front side bus also introduces transactions that are used to
deliver interrupts.
Signals on the front side bus use Assisted GTL+ (AGTL+) level voltages which are fully described
in the appropriate platform design guide (refer to
in the appropriate platform design guide (refer to
).
1.1
Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the asserted
state when driven to a low level. For example, when RESET# is low, a reset has been requested.
Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where
the name does not imply an active state but describes part of a binary sequence (such as address or
data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a
hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
state when driven to a low level. For example, when RESET# is low, a reset has been requested.
Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where
the name does not imply an active state but describes part of a binary sequence (such as address or
data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a
hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
“Front Side Bus (FSB)” refers to the electrical interface that connects the processor to the chipset.
Also referred to as the processor system bus or the system bus. All memory and I/O transactions as
well as interrupt messages pass between the processor and chipset over the FSB.
Also referred to as the processor system bus or the system bus. All memory and I/O transactions as
well as interrupt messages pass between the processor and chipset over the FSB.
1.1.1
Processor Packaging Terminology
Commonly used terms are explained here for clarification:
•
603-pin socket - The connector which mates the Intel
®
Xeon™ processor with 512 KB L2
cache to the baseboard. The 603-pin socket is a surface mount technology (SMT), zero
insertion force (ZIF) socket utilizing solder ball attachment to the platform. See the 603-Pin
Socket Design Guidelines for details regarding this socket.
insertion force (ZIF) socket utilizing solder ball attachment to the platform. See the 603-Pin
Socket Design Guidelines for details regarding this socket.
•
Central Agent - The central agent is the host bridge to the processor and is typically known as
the chipset.
the chipset.
•
Flip Chip Ball Grid Array (FCBGA) - Microprocessor packaging using “flip chip” design,
where the processor is attached to the substrate face-down for better signal integrity, more
efficient heat removal and lower inductance.
where the processor is attached to the substrate face-down for better signal integrity, more
efficient heat removal and lower inductance.
•
Front Side Bus - Front Side Bus (FSB) is the electrical interface that connects the processor to
the chipset. Also referred to as the processor system bus or the system bus. All memory and
I/O transactions as well as interrupt messages pass between the processor and chipset over the
FSB.
the chipset. Also referred to as the processor system bus or the system bus. All memory and
I/O transactions as well as interrupt messages pass between the processor and chipset over the
FSB.
•
Intel
®
Xeon™ processor with 512 KB L2 cache - The entire processor in its INT-mPGA
package, including processor core in its FC-BGA package, integrated heat spreader (IHS), and
interposer.
interposer.