Toshiba Xeon 2.8GHz UPG3843W 用户手册
产品代码
UPG3843W
Intel® Xeon™ Processor with 512 KB L2 Cache
Datasheet
19
NOTES:
1. Diagram not to scale.
2. No specifications for frequencies beyond f
2. No specifications for frequencies beyond f
core
(core frequency).
3. f
peak
, if existent, should be less than 0.05 MHz.
2.5.1
Mixing Processors
Intel only supports those processor combinations operating with the same front side bus frequency,
core frequency, VID settings, and cache sizes. Not all operating systems can support multiple
processors with mixed frequencies. Intel does not support or validate operation of processors with
different cache sizes. Mixing processors of different steppings but the same model (as per CPUID
instruction) is supported, and is outlined in the Intel® Xeon™ Processor Specification Update.
Additional details are provided in AP-485, the Intel Processor Identification and the CPUID
Instruction application note.
core frequency, VID settings, and cache sizes. Not all operating systems can support multiple
processors with mixed frequencies. Intel does not support or validate operation of processors with
different cache sizes. Mixing processors of different steppings but the same model (as per CPUID
instruction) is supported, and is outlined in the Intel® Xeon™ Processor Specification Update.
Additional details are provided in AP-485, the Intel Processor Identification and the CPUID
Instruction application note.
Unlike previous Intel® Xeon™ processors, the Intel Xeon processor with 512 KB L2 cache does
not sample the pins IGNNE#, LINT[0]/INTR, LINT[1]/NMI, and A20M# to establish the core to
front side bus ratio. Rather, the processor runs at its tested frequency at initial power-on. If the
processor needs to run at a lower core frequency, as must be done when a higher speed processor is
added to a system that contains a lower frequency processor, the system BIOS is able to effect the
change in the core to front side bus ratio.
not sample the pins IGNNE#, LINT[0]/INTR, LINT[1]/NMI, and A20M# to establish the core to
front side bus ratio. Rather, the processor runs at its tested frequency at initial power-on. If the
processor needs to run at a lower core frequency, as must be done when a higher speed processor is
added to a system that contains a lower frequency processor, the system BIOS is able to effect the
change in the core to front side bus ratio.
Figure 2. Phase Lock Loop (PLL) Filter Requirements
0 dB
-28 dB
-34 dB
0.2 dB
forbidden
zone
-0.5 dB
forbidden
zone
1 MHz
66 MHz
fcore
fpeak
1 Hz
DC
passband
high frequency
band