Toshiba Xeon 2.8GHz UPG3843W 用户手册

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1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. These parameters are based on design characterization and are not tested.
3. All AC timings for the SMBus signals are referenced at V

IL_MAX

 or V

IL_MIN

 and measured at the processor

pins. Refer to 

4. Minimum time allowed between request cycles.
5. Rise time is measured from (V

IL_MAX

 - 0.15V) to (V

IH_MIN

 + 0.15V). Fall time is measured from (0.9 *

SM_V

CC

) to (V

IL_MAX

 - 0.15V). DC parameters are specified in 

6. Following a write transaction, an internal device write cycle time of 10ms must be allowed before starting the

next transaction.

The following figures are used in conjunction with the AC timing tables, 

 through 

For 

 through 

, the following apply:

1. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage

(V

CROSS

) of the BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal

timings are referenced at GTLREF at the processor core (pads).

2. All source synchronous AC timings for AGTL+ signals are referenced to their associated

strobe (address or data) at GTLREF. Source synchronous data signals are referenced to the
falling edge of their associated data strobe. Source synchronous address signals are referenced
to the rising and falling edge of their associated address strobe. All source synchronous
AGTL+ signal timings are referenced at GTLREF at the processor core (pads).

3. All AC timings for AGTL+ strobe signals are referenced to BCLK[1:0] at V

CROSS

. All

AGTL+ strobe signal timings are referenced at GTLREF at the processor core (pads).

4. All AC Timing for he TAP signals are referenced to the TCK signal at 0.5 * V

CC

 at the

processor pins. All TAP signal timings (TMS, TDI, etc.) are referenced at the 0.5 * V

CC

 at the

processor core (pads).

5. All AC timings for the SMBus signals are referenced to the SM_CLK signal at 0.5 * SM_V

CC

at the processor pins. All SMBus signal timings (SM_DAT, SM_ALERT#, etc.) are referenced
at V

IL_MAX

 or V

IL_MIN

 at the processor pins.

T79: Bus Free Time

4.7

N/A

µS

1, 2, 3, 4, 

6

T80: Hold Time after Repeated Start Condition

4.0

N/A

µS

1, 2, 3

T81: Repeated Start Condition Setup Time

4.7

N/A

µS

1, 2, 3

T82: Stop Condition Setup Time

4.0

N/A

µS

1, 2, 3