Toshiba Xeon 2.8GHz UPG3843W 用户手册

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The Intel

® 

Xeon™ processor with 512 KB L2 cache has several configuration options that are

determined by the state of specific processor pins at the active-to-inactive transition of the
processor RESET# signal. These configuration options cannot be changed except by another reset.
Both power on and software induced resets reconfigure the processor(s). 

1. Asserting this signal during active-to-inactive edge of RESET# will selects the corresponding option.
2. The Intel® Xeon™ processor with 512 KB L2 cache does not support this feature, therefore platforms

utilizing this processor should not use these configuration pins.

3. Intel Xeon processor with 512 KB L2 cache utilize only BR0# and BR1# signals. 2-way platforms must not

utilize BR2# and BR3# signals.

The processor allows the use of AutoHALT, Stop-Grant and Sleep states to reduce power
consumption by stopping the clock to internal sections of the processor, depending on each
particular state. See 

 for a visual representation of the processor low power states.

Due to the inability of processors to recognize bus transactions during the Sleep state,
multiprocessor systems are not allowed to simultaneously have one processor in Sleep state and the
other processor in the Normal or Stop-Grant state.

This is the normal operating state for the processor.

Output tri state

SMI#

Execute BIST (Built-In Self Test)

INIT#

In Order Queue de-pipelining (set IOQ depth to 1)

A7#

Disable MCERR# observation

A9#

Disable BINIT# observation

A10#

APIC cluster ID (0-3)

A[12:11]#

2

Disable bus parking

A15#

Disable Hyper-Threading Technology

A31#

Symmetric agent arbitration ID

BR[3:0]#

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