Intel E3815 FH8065301567411 数据表
产品代码
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2333
18.7.191 Debug Capability Doorbell Register (DCDB)—Offset 8484h
Access Method
Default: 00000000h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0
RSVD
DC
ERST
M
NCP
CI
D
Bit
Range
Default &
Access
Field Name (ID): Description
31:21
000h
RO
Reserved (RSVD):
Reserved.
Power Well:
Core
20:16
05h
RW
Debug Capability Event Ring Segment Table Max (DCERSTM):
Valid values are 0
15. This field determines the maximum value supported by the Debug Capability Event
Ring Segment Table Base Size registers (see xHCI USB specification), where:
The maximum number of Event Ring Segment Table entries = 2^(DCERST Max)
e.g. if DCERST Max = 7, then the Debug Capability Event Ring Segment Table(s)
supports up to 128 entries, 15 then 32K entries, etc.
Note: This register is sticky.
Power Well:
Core
15:8
00h
RW
Next Capability Pointer (NCP):
This field indicates the location of the next capability
with respect to the effective address of this capability. Refer to the xHCI USB
specification for more information on this field. Note: This register is sticky.
Power Well:
Core
7:0
0Ah
RW
Capability ID (CID):
Refer to the xHCI USB specification for descriptions of the
capabilities listed below. Note: This register is sticky.
•
•
0 = Reserved
•
1 = USB Legacy Support
•
2 = Supported Protocol
•
3 = Extended Power Management
•
4 = I/O Virtualization
•
5 = Message Interrupt
•
6 = Local Memory
•
7-9 = Reserved
Power Well:
Core
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
DB
TG
T
RSVD
_1