Intel E3815 FH8065301567411 数据表
产品代码
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
4218
Datasheet
27.6.46
UART_BYTE_COUNT—Offset 818h
Transaction counter
Access Method
Default: 00000000h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0
RSVD
0
gp
o1
gate
r_o
ve
rrid
e
gp
o3
gp
o2
uart_374646_fix_disable
re
se
t_e
sle
ep
_
enab
le
po
we
r_e
n
ab
le
Bit
Range
Default &
Access
Field Name (ID): Description
31:8
0b
RO
RSVD0:
Reserved
7
0h
RW
gpo1:
not applicable
6
1h
RW
gater_override:
not applicable
5
0h
RW
gpo3:
not applicable
4
1h
RW
gpo2:
This bit indicates whether the UART clock req will be dynamic or controlled by the
UART clock en:
•
•
1 = controlled by the clk en
•
0 = dynamic
Default value = 1
3
0h
RW
uart_374646_fix_disable:
Disable rts_n override
2
0h
RW
reset_e:
not applicable
1
0h
RW
sleep_enable:
not applicable
0
0h
RW
power_enable:
not applicable
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:30, F:3] + 10h