Intel E3815 FH8065301567411 数据表
产品代码
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
609
Default: 00000000h
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RE
SE
RVED
IDENTIC
A
L_FRA
M
E_TH
RESH
OLD
DPLLA_POWE
R
_
D
OWN_DELA
Y
DOU
B
LE_FRAME
S_IN_P
SR_ACTIVE
_
E
N
TR
Y
SOURCE_TRANSMIT
T
E
R
_ST
A
TE
_IN_P
S
R_ACTIVE
PS
R_AC
TIVE
_E
NTR
Y
PSR_S
INGLE
_FRAME_UPDA
T
E
RESE
RVE
D
_1
PS
R_MO
DE
PSR_RE
SET
PS
R_ENA
B
LE
Bit
Range
Default &
Access
Field Name (ID): Description
31:24
0b
RW
RESERVED:
Reserved.
23:16
0b
RW
IDENTICAL_FRAME_THRESHOLD:
: Number of identical frames that display
controller needs to exceed in order to transition to PSR active state in HW timer mode
15:11
0b
RW
DPLLA_POWER_DOWN_DELAY:
programmable delay from main link powerdown to
DPLLA powerdown. The delay is in number of cdclk clocks.
10
0b
RW
DOUBLE_FRAMES_IN_PSR_ACTIVE_ENTRY:
. If asserted, HW will send two frames
with same SDP active setting when entry PSR active state. This bit is set if the vertical
blanking time is less than 330us.
9
0b
RW
SOURCE_TRANSMITTER_STATE_IN_PSR_ACTIVE:
. If asserted, HW will keep
transmitter active during PSR active state and sends only idle symbols. If deasserted,
HW will turn off transmitter during PSR active state. Display driver will keep this bit
consistent with Source transmitter state in PSR active bit in DPCD register of the sink.
8
0b
RW
PSR_ACTIVE_ENTRY:
This bit is only valid in PSR_mode is SW timer mode. If it is
asserted, HW will transition into PSR_active state. If it is deasserted, HW will transition
to PSR_inactive state. SW should not set or clear this bit more than once within one
vblank period.
7
0b
RW
PSR_SINGLE_FRAME_UPDATE:
In PSR persistent mode, SW set this bit before
writing registers for a flip. After HW finishes signle frame update, it goes back to PSR
active ? no RFB state. SW driver may send new single frame update request.
Programming note: Reading this bit is updated at the next vblank. Writing this bit to 1
will cause PSR FSM to perform single frame update automatically, no vblank is required.
When single frame update is done, it will automatically go back to PSR active ? no RFB
update. 60094[2:0] = 3b011.
6:5
0b
RW
RESERVED_1:
Reserved.