Renesas M32R-FPU 用户手册
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M32R-FPU Software Manual (Rev.1.01)
1.7 Addressing Mode
M32R-FPU supports the following addressing modes.
(1) Register direct [R or CR]
The general-purpose register or the control register to be processed is
specified.
specified.
(2) Register indirect [@R]
The contents of the register specify the address of the memory. This mode
can be used by all load/store instructions.
can be used by all load/store instructions.
(3) Register relative indirect [@(disp, R)]
(The contents of the register) + (16-bit immediate value which is sign-
extended to 32 bits) specify the address of the memory.
(4) Register indirect and register update
• Adds 4 to register contents [@R+]
The contents of the register specify the memory address, then 4 is added to
the register contents.
(Can only be specified with LD instruction).
the register contents.
(Can only be specified with LD instruction).
• Add 2 to register contents [@R+] [M32R-FPU extended addressing mode]
The contents of the register specify the memory address, then 2 is added to
the register contents.
the register contents.
(Can only be specified with STH instruction).
• Add 4 to register contents [@+R]
The contents of the register is added by 4, the register contents specify the
memory address.
(Can only be specified with ST instruction).
memory address.
(Can only be specified with ST instruction).
• Subtract 4 to register contents [@–R]
The content of the register is decreased by 4, then the register contents
specify the memory address.
(Can only be specified with ST instruction).
specify the memory address.
(Can only be specified with ST instruction).
(5) immediate [#imm]
The 4-, 5-, 8-, 16- or 24-bit immediate value.
(6) PC relative [pcdisp]
(The contents of PC) + (8, 16, or 24-bit displacement which is sign-extended
to 32 bits and 2 bits left-shifted) specify the address of memory.
CPU PROGRAMMING MODEL
1.7 Addressing Mode