用户手册 — Atmel SAM4L Xplained Pro Starter Kit Atmel ATSAM4L-XSTK

Atmel

产品代码

ATSAM4L-XSTK

数据表 (English)数据表 (English)数据表 (English)数据表 (English)

数据表 (ATSAM4L-XSTK)

目录

数据表 (ATSAM4L-XSTK)

文件大小：

890.8 KB
页数：

20
Language:

English

打开用户手册

数据表 (ATSAM4L-XSTK)

目录

数据表 (ATSAM4L-XSTK)

文件大小：

2.7 MB
页数：

173
Language:

English

打开用户手册

数据表 (ATSAM4L-XSTK)

目录

Summary
1
Features
1
1. Description
3
2. Overview
5
- 2.1 Block Diagram
  5
- 2.2 Configuration Summary
  6
3. Package and Pinout
8
- 3.1 Package
  8
  - 3.1.1 ATSAM4LCx Pinout
    8
  - 3.1.2 ATSAM4LSx Pinout
    13
- 3.2 Peripheral Multiplexing on I/O lines
  18
- 3.3 Signals Description
  30
- 3.4 I/O Line Considerations
  33
  - 3.4.1 SW/JTAG Pins
    33
  - 3.4.2 RESET_N Pin
    33
  - 3.4.3 TWI Pins
    33
  - 3.4.4 GPIO Pins
    33
  - 3.4.5 High-drive Pins
    33
  - 3.4.6 USB Pins
    33
  - 3.4.7 ADC Input Pins
    34
4. Cortex-M4 processor and core peripherals
35
- 4.1 Cortex-M4
  35
- 4.2 System level interface
  36
- 4.3 Integrated configurable debug
  36
- 4.4 Cortex-M4 processor features and benefits summary
  37
- 4.5 Cortex-M4 core peripherals
  37
- 4.6 Cortex-M4 implementations options
  38
- 4.7 Cortex-M4 Interrupts map
  38
- 4.8 Peripheral Debug
  41
  - 4.8.1 Peripheral Debug
    41
5. Power and Startup Considerations
42
- 5.1 Power Domain Overview
  42
- 5.2 Power Supplies
  44
- 5.3 Startup Considerations
  49
  - 5.3.1 Starting of Clocks
    49
  - 5.3.2 Fetching of Initial Instructions
    49
- 5.4 Power-on-Reset, Brownout and Supply Monitor
  49
6. Low Power Techniques
51
- 6.1 Power Save Modes
  51
- 6.2 Power Scaling
  56
7. Memories
58
- 7.1 Product Mapping
  58
- 7.2 Embedded Memories
  59
- 7.3 Physical Memory Map
  59
8. Debug and Test
61
- 8.1 Features
  61
- 8.2 Overview
  61
- 8.3 Block Diagram
  62
- 8.4 I/O Lines Description
  62
- 8.5 Product Dependencies
  63
  - 8.5.1 I/O Lines
    63
  - 8.5.2 Power Management
    63
  - 8.5.3 Clocks
    63
- 8.6 Core Debug
  63
- 8.7 Enhanced Debug Port (EDP)
  66
- 8.8 System Manager Access Port (SMAP)
  76
- 8.9 AHB-AP Access Port
  91
- 8.10 Available Features in Protected State
  92
- 8.11 Functional Description
  93
9. Chip Identifier (CHIPID)
98
- 9.1 Description
  98
- 9.2 Embedded Characteristics
  98
- 9.3 User Interface
  100
  - 9.3.1 Chip ID Register
    101
  - 9.3.2 Extension Register
    106
10. Power Manager (PM)
108
- 10.1 Features
  108
- 10.2 Overview
  108
- 10.3 Block Diagram
  108
- 10.4 I/O Lines Description
  109
- 10.5 Product Dependencies
  109
  - 10.5.1 Interrupt
    109
  - 10.5.2 Clock Implementation
    109
- 10.6 Functional Description
  109
- 10.7 User Interface
  115
- 10.8 Module Configuration
  138
11. Backup Power Manager (BPM)
139
- 11.1 Features
  139
- 11.2 Overview
  139
- 11.3 Block Diagram
  140
- 11.4 Product Dependencies
  140
  - 11.4.1 Clocks
    140
  - 11.4.2 Interrupts
    141
  - 11.4.3 Debug Operation
    141
- 11.5 Functional Description
  141
- 11.6 User Interface
  144
- 11.7 Module Configuration
  159
12. Backup System Control Interface (BSCIF)
160
- 12.1 Features
  160
- 12.2 Overview
  160
- 12.3 Block Diagram
  161
- 12.4 I/O Lines Description
  161
- 12.5 Product Dependencies
  162
  - 12.5.1 Power Management
    162
  - 12.5.2 Clocks
    162
  - 12.5.3 Interrupts
    162
  - 12.5.4 Debug Operation
    162
- 12.6 Functional Description
  162
  - 12.6.1 32 KHz Oscillator (OSC32K) Operation
    162
  - 12.6.2 32 KHz RC Oscillator (RC32K)
    163
  - 12.6.3 Brow-Out Detector (BOD) Operation
    164
    - 12.6.3.1 Monitored Voltages
      165
    - 12.6.3.2 Supported Modes
      165
    - 12.6.3.3 Continuous Mode
      166
    - 12.6.3.4 Sampling Mode
      166
    - 12.6.3.5 Clock Sources
      166
    - 12.6.3.6 Changing Clock Source
      167
    - 12.6.3.7 Changing the Prescaler
      167
    - 12.6.3.8 BOD18/33 Interrupts/Reset
      167
    - 12.6.3.9 Hysteresis
      167
    - 12.6.3.10 BOD18 Threshold Ranges
      167
    - 12.6.3.11 Power Save Modes
      168
    - 12.6.3.12 Flash Fuses
      168
  - 12.6.4 Voltage Regulator (VREG)
    168
    - 12.6.4.1 Register Protection
      168
    - 12.6.4.2 1MHz RC Oscillator
      169
  - 12.6.5 Bandgap
    169
  - 12.6.6 Backup Registers (BR)
    169
  - 12.6.7 Interrupts
    169
- 12.7 User Interface
  171
- 12.8 Module Configuration
  201
13. System Control Interface (SCIF)
202
- 13.1 Features
  202
- 13.2 Overview
  202
- 13.3 Block Diagram
  202
- 13.4 I/O Lines Description
  203
- 13.5 Product Dependencies
  203
  - 13.5.1 I/O Lines
    203
  - 13.5.2 Power Management
    203
  - 13.5.3 Clocks
    203
  - 13.5.4 Interrupts
    203
  - 13.5.5 Debug Operation
    203
- 13.6 Functional Description
  203
- 13.7 User Interface
  219
- 13.8 Module Configuration
  258
14. Flash Controller (FLASHCALW)
262
- 14.1 Features
  262
- 14.2 Overview
  262
- 14.3 Block Diagram
  263
- 14.4 Product Dependencies
  263
  - 14.4.1 Power Management
    263
  - 14.4.2 Clocks
    263
  - 14.4.3 Interrupts
    264
  - 14.4.4 Debug Operation
    264
- 14.5 Functional Description
  265
- 14.6 Flash Commands
  274
- 14.7 General-purpose Fuse Bits
  276
- 14.8 Security Fuses
  277
- 14.9 Error Correcting Code
  277
- 14.10 User Interface
  279
- 14.11 Fuse Settings
  298
- 14.12 Serial Number
  302
- 14.13 Module Configuration
  302
15. HSB Bus Matrix (HMATRIXB)
304
- 15.1 Features
  304
- 15.2 Overview
  304
- 15.3 Product Dependencies
  304
  - 15.3.1 Clocks
    304
- 15.4 Functional Description
  304
- 15.5 User Interface
  308
- 15.6 Module Configuration
  316
  - 15.6.1 Bus Matrix Connections
    316
16. Peripheral DMA Controller (PDCA)
318
- 16.1 Features
  318
- 16.2 Overview
  318
- 16.3 Block Diagram
  319
- 16.4 Product Dependencies
  319
  - 16.4.1 Power Management
    319
  - 16.4.2 Clocks
    319
  - 16.4.3 Interrupts
    319
  - 16.4.4 Peripheral Events
    320
- 16.5 Functional Description
  320
  - 16.5.1 Basic Operation
    320
  - 16.5.2 Memory Pointer
    320
  - 16.5.3 Transfer Counter
    320
  - 16.5.4 Reload Registers
    320
  - 16.5.5 Ring Buffer
    321
  - 16.5.6 Peripheral Selection
    321
  - 16.5.7 Transfer Size
    321
  - 16.5.8 Enabling and Disabling
    321
  - 16.5.9 Interrupts
    321
  - 16.5.10 Priority
    322
  - 16.5.11 Error Handling
    322
  - 16.5.12 Peripheral Event Trigger
    322
- 16.6 User Interface
  323
- 16.7 Module Configuration
  337
17. USB Device and Embedded Host Interface (USBC)
340
- 17.1 Features
  340
- 17.2 Overview
  340
- 17.3 Block Diagram
  340
- 17.4 I/O Lines Description
  342
- 17.5 Product Dependencies
  343
  - 17.5.1 I/O Lines
    343
  - 17.5.2 Power Management
    343
  - 17.5.3 Clocks
    343
  - 17.5.4 Interrupts
    343
- 17.6 Functional Description
  344
  - 17.6.1 USB General Operation
    344
    - 17.6.1.1 Initialization
      344
    - 17.6.1.2 Interrupts
      345
    - 17.6.1.3 Frozen clock
      345
    - 17.6.1.4 Speed control
      345
      - • Device mode
        345
      - • Host mode
        345
    - 17.6.1.5 Data management
      345
    - 17.6.1.6 Pad Suspend
      346
  - 17.6.2 USBC Device Mode Operation
    347
    - 17.6.2.1 Device Enabling
      347
    - 17.6.2.2 USB reset
      347
    - 17.6.2.3 Endpoint activation
      347
    - 17.6.2.4 Endpoint redirection
      347
    - 17.6.2.5 Data toggle sequence
      347
    - 17.6.2.6 Busy bank enable
      348
    - 17.6.2.7 Address setup
      348
    - 17.6.2.8 Suspend and Wakeup
      348
    - 17.6.2.9 Detach
      348
    - 17.6.2.10 Remote wakeup
      349
    - 17.6.2.11 RAM management
      349
    - 17.6.2.12 STALL request
      351
      - • Special considerations for control endpoints
        351
      - • STALL handshake and retry mechanism
        351
    - 17.6.2.13 Multi packet mode and single packet mode.
      352
    - 17.6.2.14 Management of control endpoints
      352
      - • Overview
        352
      - • Control write
        352
      - • Control read
        353
    - 17.6.2.15 Management of IN endpoints
      354
      - • Overview
        354
      - • Detailed description
        355
      - • Multi packet mode for IN endpoints
        355
    - 17.6.2.16 Management of OUT endpoints
      356
      - • Overview
        356
      - • Detailed description
        357
      - • Multi packet mode for OUT endpoints
        357
    - 17.6.2.17 Data flow error
      358
    - 17.6.2.18 CRC error
      358
    - 17.6.2.19 Interrupts
      358
      - • Global interrupts
        358
      - • Endpoint interrupts
        359
  - 17.6.3 USB Host Operation
    360
    - 17.6.3.1 Host Enabling
      360
    - 17.6.3.2 Device detection
      360
    - 17.6.3.3 Description of pipes
      360
    - 17.6.3.4 USB reset
      361
    - 17.6.3.5 Pipe activation
      361
    - 17.6.3.6 Address setup
      361
    - 17.6.3.7 Remote wakeup
      362
    - 17.6.3.8 RAM management
      362
    - 17.6.3.9 Multi packet mode and single packet mode.
      365
    - 17.6.3.10 Management of control pipes
      365
    - 17.6.3.11 Management of IN pipes
      365
      - • Overview
        365
      - • Detailed description
        365
      - • Multi packet mode for IN pipes
        366
    - 17.6.3.12 Management of OUT pipes
      366
      - • Overview
        366
      - • Detailed description
        366
      - • Multi packet mode for OUT pipes
        368
    - 17.6.3.13 Alternate pipe
      368
    - 17.6.3.14 Data flow error
      368
    - 17.6.3.15 CRC error
      368
    - 17.6.3.16 Interrupts
      369
      - • Global interrupts
        369
      - • Pipe interrupts
        369
- 17.7 User Interface
  370
- 17.8 Module Configuration
  427
18. Advanced Encryption Standard (AESA)
428
- 18.1 Features
  428
- 18.2 Overview
  428
- 18.3 Product Dependencies
  429
  - 18.3.1 Power Management
    429
  - 18.3.2 Clocks
    429
  - 18.3.3 Interrupts
    429
- 18.4 Functional Description
  429
- 18.5 User Interface
  434
  - 18.5.1 Control Register
    435
  - 18.5.2 Mode Register
    436
  - 18.5.3 Data Buffer Pointer Register
    438
  - 18.5.4 Status Register
    439
  - 18.5.5 Interrupt Enable Register
    440
  - 18.5.6 Interrupt Disable Register
    441
  - 18.5.7 Interrupt Mask Register
    442
  - 18.5.8 Key Registers
    443
  - 18.5.9 Initialization Vector Registers
    444
  - 18.5.10 Input Data Register
    445
  - 18.5.11 Output Data Register
    446
  - 18.5.12 DRNG Seed Register
    447
  - 18.5.13 Parameter Register
    448
  - 18.5.14 Version Register
    449
- 18.6 Module Configuration
  450
19. Asynchronous Timer (AST)
451
- 19.1 Features
  451
- 19.2 Overview
  451
- 19.3 Block Diagram
  452
- 19.4 Product Dependencies
  452
  - 19.4.1 Power Management
    452
  - 19.4.2 Clocks
    452
  - 19.4.3 Interrupts
    453
  - 19.4.4 Peripheral Events
    453
  - 19.4.5 Debug Operation
    453
- 19.5 Functional Description
  453
  - 19.5.1 Initialization
    453
    - 19.5.1.1 Enabling and Disabling the AST Clock
      453
    - 19.5.1.2 Changing the Source Clock
      454
  - 19.5.2 Basic Operation
    454
    - 19.5.2.1 Prescaler
      454
    - 19.5.2.2 Counter Operation
      454
    - 19.5.2.3 Calendar Operation
      455
  - 19.5.3 Interrupts
    455
    - 19.5.3.1 Periodic Interrupt
      455
    - 19.5.3.2 Alarm Interrupt
      456
  - 19.5.4 Peripheral Events
    456
  - 19.5.5 AST wakeup
    457
  - 19.5.6 Backup Mode
    457
  - 19.5.7 Digital Tuner
    457
  - 19.5.8 Synchronization
    458
- 19.6 User Interface
  459
  - 19.6.1 Control Register
    460
  - 19.6.2 Counter Value
    461
  - 19.6.3 Status Register
    462
  - 19.6.4 Status Clear Register
    463
  - 19.6.5 Interrupt Enable Register
    464
  - 19.6.6 Interrupt Disable Register
    465
  - 19.6.7 Interrupt Mask Register
    466
  - 19.6.8 Wake Enable Register
    467
  - 19.6.9 Alarm Register 0
    468
  - 19.6.10 Alarm Register 1
    469
  - 19.6.11 Periodic Interval Register 0
    470
  - 19.6.12 Periodic Interval Register 1
    471
  - 19.6.13 Clock Control Register
    472
  - 19.6.14 Digital Tuner Register
    473
  - 19.6.15 Event Enable Register
    474
  - 19.6.16 Event Disable Register
    475
  - 19.6.17 Event Mask Register
    476
  - 19.6.18 Calendar Value
    477
  - 19.6.19 Parameter Register
    478
  - 19.6.20 Version Register
    479
- 19.7 Module Configuration
  480
20. Watchdog Timer (WDT)
481
- 20.1 Features
  481
- 20.2 Overview
  481
- 20.3 Block Diagram
  481
- 20.4 Product Dependencies
  481
  - 20.4.1 Power Management
    482
  - 20.4.2 Clocks
    482
  - 20.4.3 Interrupt
    482
  - 20.4.4 Debug Operation
    482
  - 20.4.5 Fuses
    482
- 20.5 Functional Description
  482
  - 20.5.1 Basic Mode
    482
  - 20.5.2 Window Mode
    484
  - 20.5.3 Interrupt Mode
    486
  - 20.5.4 Disabling the WDT
    488
  - 20.5.5 Flash Calibration
    488
  - 20.5.6 Special Considerations
    488
  - 20.5.7 Interrupts
    488
- 20.6 User Interface
  489
  - 20.6.1 Control Register
    490
  - 20.6.2 Clear Register
    492
  - 20.6.3 Status Register
    493
  - 20.6.4 Interrupt Enable Register
    494
  - 20.6.5 Interrupt Disable Register
    495
  - 20.6.6 Interrupt Mask Register
    496
  - 20.6.7 Interrupt Status Register
    497
  - 20.6.8 Interrupt Clear Register
    498
  - 20.6.9 Version Register
    499
- 20.7 Module Configuration
  500
21. External Interrupt Controller (EIC)
501
- 21.1 Features
  501
- 21.2 Overview
  501
- 21.3 Block Diagram
  501
- 21.4 I/O Lines Description
  502
- 21.5 Product Dependencies
  502
  - 21.5.1 I/O Lines
    502
  - 21.5.2 Power Management
    502
  - 21.5.3 Clocks
    502
  - 21.5.4 Interrupts
    502
  - 21.5.5 Debug Operation
    502
- 21.6 Functional Description
  502
- 21.7 User Interface
  506
  - 21.7.1 Interrupt Enable Register
    507
  - 21.7.2 Interrupt Disable Register
    508
  - 21.7.3 Interrupt Mask Register
    509
  - 21.7.4 Interrupt Status Register
    510
  - 21.7.5 Interrupt Clear Register
    511
  - 21.7.6 Mode Register
    512
  - 21.7.7 Edge Register
    513
  - 21.7.8 Level Register
    514
  - 21.7.9 Filter Register
    515
  - 21.7.10 Test Register
    516
  - 21.7.11 Asynchronous Register
    517
  - 21.7.12 Enable Register
    518
  - 21.7.13 Disable Register
    519
  - 21.7.14 Control Register
    520
  - 21.7.15 Version Register
    521
- 21.8 Module Configuration
  522
22. Frequency Meter (FREQM)
523
- 22.1 Features
  523
- 22.2 Overview
  523
- 22.3 Block Diagram
  523
- 22.4 Product Dependencies
  523
  - 22.4.1 Power Management
    523
  - 22.4.2 Clocks
    524
  - 22.4.3 Debug Operation
    524
  - 22.4.4 Interrupts
    524
- 22.5 Functional Description
  524
  - 22.5.1 Reference Clock
    524
    - 22.5.1.1 Cautionary Note
      525
  - 22.5.2 Measurement
    525
  - 22.5.3 Interrupts
    525
- 22.6 User Interface
  526
  - 22.6.1 Control Register
    527
  - 22.6.2 Mode Register
    528
  - 22.6.3 Status Register
    529
  - 22.6.4 Value Register
    530
  - 22.6.5 Interrupt Enable Register
    531
  - 22.6.6 Interrupt Disable Register
    532
  - 22.6.7 Interrupt Mask Register
    533
  - 22.6.8 Interrupt Status Register
    534
  - 22.6.9 Interrupt Clear Register
    535
  - 22.6.10 Version Register
    536
- 22.7 Module Configuration
  537
23. General-Purpose Input/Output Controller (GPIO)
539
- 23.1 Features
  539
- 23.2 Overview
  539
- 23.3 Block Diagram
  539
- 23.4 I/O Lines Description
  540
- 23.5 Product Dependencies
  540
  - 23.5.1 Power Management
    540
  - 23.5.2 Clocks
    540
  - 23.5.3 Interrupts
    540
  - 23.5.4 Peripheral Events
    540
  - 23.5.5 Debug Operation
    540
- 23.6 Functional Description
  541
  - 23.6.1 Basic Operation
    542
    - 23.6.1.1 Module Configuration
      542
    - 23.6.1.2 Available Features
      542
    - 23.6.1.3 Inputs
      542
    - 23.6.1.4 Output Control
      542
    - 23.6.1.5 Peripheral Muxing
      542
  - 23.6.2 Advanced Operation
    543
- 23.7 User Interface
  547
- 23.8 Module Configuration
  572
24. Universal Synchronous Asynchronous Receiver Transmitter (USART)
574
- 24.1 Features
  574
- 24.2 Overview
  574
- 24.3 Block Diagram
  575
- 24.4 I/O Lines Description
  577
- 24.5 Product Dependencies
  577
  - 24.5.1 I/O Lines
    577
  - 24.5.2 Clocks
    577
  - 24.5.3 Interrupts
    577
- 24.6 Functional Description
  578
- 24.7 User Interface
  621
- 24.8 Module Configuration
  651
25. Picopower UART (PICOUART)
652
- 25.1 Features
  652
- 25.2 Overview
  652
- 25.3 Block Diagram
  652
- 25.4 I/O Lines Description
  653
- 25.5 Product Dependencies
  653
  - 25.5.1 I/O Lines
    653
  - 25.5.2 Power Management
    653
  - 25.5.3 Clocks
    653
  - 25.5.4 Backup Power Management
    653
  - 25.5.5 Peripheral Events
    653
- 25.6 Functional Description
  653
- 25.7 User Interface
  656
  - 25.7.1 Control Register
    657
  - 25.7.2 Configuration Register
    658
  - 25.7.3 Status Register
    659
  - 25.7.4 Receive Holding Register
    660
  - 25.7.5 Version Register
    661
- 25.8 Module Configuration
  662
26. Serial Peripheral Interface (SPI)
663
- 26.1 Features
  663
- 26.2 Overview
  663
- 26.3 Block Diagram
  664
- 26.4 Application Block Diagram
  664
- 26.5 I/O Lines Description
  665
- 26.6 Product Dependencies
  665
  - 26.6.1 I/O Lines
    665
  - 26.6.2 Clocks
    665
  - 26.6.3 Interrupts
    665
- 26.7 Functional Description
  665
- 26.8 User Interface
  676
- 26.9 Module Configuration
  703
27. Two-wire Master Interface (TWIM)
704
- 27.1 Features
  704
- 27.2 Overview
  704
- 27.3 List of Abbreviations
  705
- 27.4 Block Diagram
  705
- 27.5 Application Block Diagram
  706
- 27.6 I/O Lines Description
  706
- 27.7 Product Dependencies
  706
  - 27.7.1 I/O Lines
    706
  - 27.7.2 Power Management
    706
  - 27.7.3 Clocks
    707
  - 27.7.4 DMA
    707
  - 27.7.5 Interrupts
    707
  - 27.7.6 Debug Operation
    707
- 27.8 Functional Description
  708
- 27.9 User Interface
  722
- 27.10 Module Configuration
  742
28. Two-wire Slave Interface (TWIS)
743
- 28.1 Features
  743
- 28.2 Overview
  743
- 28.3 List of Abbreviations
  744
- 28.4 Block Diagram
  744
- 28.5 Application Block Diagram
  745
- 28.6 I/O Lines Description
  745
- 28.7 Product Dependencies
  745
  - 28.7.1 I/O Lines
    745
  - 28.7.2 Power Management
    745
  - 28.7.3 Clocks
    746
  - 28.7.4 DMA
    746
  - 28.7.5 Interrupts
    746
  - 28.7.6 Debug Operation
    746
- 28.8 Functional Description
  746
- 28.9 User Interface
  757
- 28.10 Module Configuration
  776
29. Inter-IC Sound Controller (IISC)
777
- 29.1 Features
  777
- 29.2 Overview
  777
- 29.3 Block Diagram
  778
- 29.4 I/O Lines Description
  778
- 29.5 Product Dependencies
  778
  - 29.5.1 I/O lines
    778
  - 29.5.2 Power Management
    778
  - 29.5.3 Clocks
    779
  - 29.5.4 DMA
    779
  - 29.5.5 Interrupts
    779
  - 29.5.6 Debug Operation
    779
- 29.6 Functional Description
  779
  - 29.6.1 Initialization
    779
  - 29.6.2 Basic Operation
    779
  - 29.6.3 Master, Controller, and Slave Modes
    780
  - 29.6.4 I2S Reception and Transmission Sequence
    780
  - 29.6.5 Serial Clock and Word Select Generation
    781
  - 29.6.6 Mono
    782
  - 29.6.7 Holding Registers
    782
  - 29.6.8 DMA Operation
    783
  - 29.6.9 Loop-back Mode
    783
  - 29.6.10 Interrupts
    783
- 29.7 IISC Application Examples
  784
- 29.8 User Interface
  786
  - 29.8.1 Control Register
    787
  - 29.8.2 Mode Register
    788
  - 29.8.3 Status Register
    790
  - 29.8.4 Status Clear Register
    791
  - 29.8.5 Status Set Register
    792
  - 29.8.6 Interrupt Enable Register
    793
  - 29.8.7 Interrupt Disable Register
    794
  - 29.8.8 Interrupt Mask Register
    795
  - 29.8.9 Receive Holding Register
    796
  - 29.8.10 Transmit Holding Register
    797
  - 29.8.11 Module Version
    798
  - 29.8.12 Module Parameters
    799
- 29.9 Module Configuration
  800
30. Timer/Counter (TC)
801
- 30.1 Features
  801
- 30.2 Overview
  801
- 30.3 Block Diagram
  802
- 30.4 I/O Lines Description
  802
- 30.5 Product Dependencies
  802
  - 30.5.1 I/O Lines
    802
  - 30.5.2 Power Management
    803
  - 30.5.3 Clocks
    803
  - 30.5.4 Interrupts
    803
  - 30.5.5 Peripheral Events
    803
  - 30.5.6 Debug Operation
    803
- 30.6 Functional Description
  803
  - 30.6.1 TC Description
    803
    - 30.6.1.1 Channel I/O Signals
      803
    - 30.6.1.2 16-bit counter
      803
    - 30.6.1.3 Clock selection
      804
    - 30.6.1.4 Clock control
      805
    - 30.6.1.5 TC operating modes
      806
    - 30.6.1.6 Trigger
      806
    - 30.6.1.7 Peripheral events on TIOA/TIOB inputs
      807
  - 30.6.2 Capture Operating Mode
    807
    - 30.6.2.1 Capture registers A and B
      807
    - 30.6.2.2 Trigger conditions
      807
  - 30.6.3 Waveform Operating Mode
    809
    - 30.6.3.1 Waveform selection
      809
    - 30.6.3.2 WAVSEL = 0
      811
    - 30.6.3.3 WAVSEL = 2
      812
    - 30.6.3.4 WAVSEL = 1
      813
    - 30.6.3.5 WAVSEL = 3
      815
    - 30.6.3.6 External event/trigger conditions
      816
    - 30.6.3.7 Output controller
      816
- 30.7 2-bit Gray Up/Down Counter for Stepper Motor
  817
- 30.8 Write Protection System
  817
- 30.9 User Interface
  818
- 30.10 Module Configuration
  843
31. Peripheral Event Controller (PEVC)
844
- 31.1 Features
  844
- 31.2 Overview
  844
- 31.3 Block Diagram
  845
- 31.4 I/O Lines Description
  846
- 31.5 Product Dependencies
  846
  - 31.5.1 I/O Lines
    846
  - 31.5.2 Power Management and Low Power Operation
    846
  - 31.5.3 Clocks
    847
  - 31.5.4 Interrupts
    848
  - 31.5.5 Debug Operation
    848
- 31.6 Functional Description
  849
- 31.7 Application Example
  851
- 31.8 User Interface
  852
- 31.9 Module Configuration
  873
32. Audio Bit Stream DAC (ABDACB)
876
- 32.1 Features
  876
- 32.2 Overview
  876
- 32.3 Block Diagram
  876
- 32.4 I/O Lines Description
  877
- 32.5 Product Dependencies
  877
  - 32.5.1 I/O lines
    877
  - 32.5.2 Clocks
    877
  - 32.5.3 DMA
    877
  - 32.5.4 Interrupts
    877
- 32.6 Functional Description
  878
  - 32.6.1 Construction
    878
  - 32.6.2 Initialization
    878
  - 32.6.3 Basic operation
    879
  - 32.6.4 Data Format
    879
  - 32.6.5 Data Swapping
    879
  - 32.6.6 Common Mode Offset Control
    879
  - 32.6.7 Volume Control
    880
  - 32.6.8 Mono
    881
  - 32.6.9 Alternative Upsampling Ratio
    881
  - 32.6.10 DMA operation
    881
  - 32.6.11 Interrupts
    881
  - 32.6.12 Frequency Response
    882
- 32.7 User Interface
  885
- 32.8 Module Configuration
  899
33. Digital to Analog Converter Controller (DACC)
900
- 33.1 Features
  900
- 33.2 Overview
  900
- 33.3 Block Diagram
  901
- 33.4 Signal Description
  901
- 33.5 Product Dependencies
  901
  - 33.5.1 Clocks
    901
  - 33.5.2 Interrupt Sources
    902
- 33.6 Functional Description
  902
- 33.7 User Interface
  904
- 33.8 Module Configuration
  915
34. Capacitive Touch Module (CATB)
916
- 34.1 Features
  916
- 34.2 Overview
  916
- 34.3 Block Diagram
  917
- 34.4 I/O Lines Description
  917
- 34.5 Product Dependencies
  917
  - 34.5.1 I/O Lines
    917
  - 34.5.2 Power Management
    917
  - 34.5.3 Clocks
    917
  - 34.5.4 Interrupts
    918
  - 34.5.5 Direct Memory Access
    918
  - 34.5.6 Debug Operation
    918
- 34.6 Functional Description
  918
- 34.7 User Interface
  927
- 34.8 Module Configuration
  949
35. True Random Number Generator (TRNG)
950
- 35.1 Features
  950
- 35.2 Overview
  950
- 35.3 Functional Description
  950
- 35.4 User Interface
  951
- 35.5 Module Configuration
  959
36. Glue Logic Controller (GLOC)
960
- 36.1 Features
  960
- 36.2 Overview
  960
- 36.3 Block Diagram
  960
- 36.4 I/O Lines Description
  961
- 36.5 Product Dependencies
  961
  - 36.5.1 I/O Lines
    961
  - 36.5.2 Clocks
    961
  - 36.5.3 Debug Operation
    961
- 36.6 Functional Description
  961
- 36.7 User Interface
  963
  - 36.7.1 Control Register n
    964
  - 36.7.2 Truth Table Register n
    965
  - 36.7.3 Parameter Register
    966
  - 36.7.4 Version Register
    967
- 36.8 Module Configuration
  968
37. Analog Comparator Interface (ACIFC)
969
- 37.1 Features
  969
- 37.2 Overview
  969
- 37.3 Block Diagram
  970
- 37.4 I/O Lines Description
  970
- 37.5 Product Dependencies
  971
  - 37.5.1 I/O Lines
    971
  - 37.5.2 Power Management
    971
  - 37.5.3 Clocks
    971
  - 37.5.4 Interrupts
    971
  - 37.5.5 Peripheral Events
    971
  - 37.5.6 Debug Operation
    971
- 37.6 Functional Description
  971
- 37.7 Peripheral Event Triggers
  977
- 37.8 AC Test mode
  977
- 37.9 User Interface
  978
- 37.10 Module configuration
  993
38. ADC Interface (ADCIFE)
994
- 38.1 Features
  994
- 38.2 Overview
  994
- 38.3 Block diagram
  995
- 38.4 I/O Lines Description
  995
- 38.5 Product dependencies
  995
  - 38.5.1 I/O Lines
    995
  - 38.5.2 Power Management
    996
  - 38.5.3 Clocks
    996
  - 38.5.4 Interrupt Controller
    996
  - 38.5.5 Event System
    996
- 38.6 Section 42. ”Electrical Characteristics” on page 1120Functional Description
  996
  - 38.6.1 Initializing the ADCIFE
    996
  - 38.6.2 Basic Operation
    997
  - 38.6.3 ADC Resolution
    997
  - 38.6.4 Differential and Single-Ended Conversion Modes
    997
  - 38.6.5 ADC Clock Configuration
    998
  - 38.6.6 Power Reduction Mode
    998
  - 38.6.7 Power-up and Startup Time
    998
  - 38.6.8 Operation Start/Stop
    998
  - 38.6.9 Analog Reference
    999
  - 38.6.10 GAIN
    999
  - 38.6.11 Conversion Results
    999
  - 38.6.12 Operating Modes Overview
    999
  - 38.6.13 Sequencer Trigger Event (STRIG)
    1000
  - 38.6.14 Internal Timer
    1000
  - 38.6.15 Peripheral DMA Controller (PDCA) Capability
    1001
  - 38.6.16 Zoom Mode
    1002
  - 38.6.17 Window Monitor
    1002
  - 38.6.18 Interrupts
    1003
  - 38.6.19 Conversion Performances
    1003
- 38.7 User Interface
  1004
  - 38.7.1 Control Register
    1005
  - 38.7.2 Configuration Register
    1007
  - 38.7.3 Status Register
    1009
  - 38.7.4 Status Clear Register
    1011
  - 38.7.5 Sequencer Configuration Register
    1012
  - 38.7.6 Configuration Direct Memory Access
    1017
  - 38.7.7 Timing Configuration Register
    1019
  - 38.7.8 Internal Timer Register
    1020
  - 38.7.9 Window Monitor Configuration
    1021
  - 38.7.10 Window Monitor Threshold Configuration
    1022
  - 38.7.11 Sequencer Last Converted Value
    1023
  - 38.7.12 Interrupt Enable Register
    1024
  - 38.7.13 Interrupt Disable Register
    1025
  - 38.7.14 Interrupt Mask Register
    1026
  - 38.7.15 Calibration Register
    1027
  - 38.7.16 Module Version
    1029
  - 38.7.17 Parameter Register
    1030
- 38.8 Module Configuration
  1031
39. LCD Controller (LCDCA)
1032
- 39.1 Features
  1032
- 39.2 Overview
  1032
- 39.3 Block Diagram
  1033
- 39.4 I/O Lines Description
  1033
- 39.5 Product Dependencies
  1033
  - 39.5.1 I/O Lines
    1034
  - 39.5.2 Power Management
    1034
  - 39.5.3 Clocks
    1034
  - 39.5.4 Interrupts
    1034
  - 39.5.5 Wake Up
    1034
  - 39.5.6 Debug Operation
    1034
- 39.6 Functional Description
  1034
  - 39.6.1 LCD Display
    1034
  - 39.6.2 Operating modes
    1035
    - 39.6.2.1 Static Duty and Static Bias
      1035
    - 39.6.2.2 1/2 Duty and 1/3 Bias
      1036
    - 39.6.2.3 1/3 Duty and 1/3 Bias
      1036
    - 39.6.2.4 1/4 Duty and 1/3 Bias
      1037
  - 39.6.3 Enabling/Disabling LCDCA
    1037
  - 39.6.4 Waveform Modes
    1038
  - 39.6.5 Timing Generation
    1038
    - 39.6.5.1 Frame Rate
      1038
    - 39.6.5.2 Frame Counters
      1039
  - 39.6.6 CPU Display Memory Access
    1040
    - 39.6.6.1 Direct Access
      1040
    - 39.6.6.2 Indirect Access
      1040
  - 39.6.7 Locking Shadow Display Memory
    1040
  - 39.6.8 Blinking Modes
    1040
    - 39.6.8.1 Software Blinking
      1040
    - 39.6.8.2 Hardware Blinking
      1040
  - 39.6.9 Autonomous Segment Animation
    1041
  - 39.6.10 ASCII Character Mapping
    1042
  - 39.6.11 Automated Character Mapping
    1047
    - 39.6.11.1 Sequential Characters String Display
      1047
    - 39.6.11.2 Scrolling of Characters String
      1048
  - 39.6.12 Automated Bit Mapping
    1049
  - 39.6.13 Contrast Adjustment
    1050
  - 39.6.14 Interrupts
    1050
  - 39.6.15 LCD Wake Up
    1050
  - 39.6.16 LCD Power Supply
    1051
- 39.7 User Interface
  1053
- 39.8 Module Configuration
  1077
40. Parallel Capture (PARC)
1080
- 40.1 Features
  1080
- 40.2 Overview
  1080
- 40.3 Block Diagram
  1080
- 40.4 I/O Lines Description
  1080
- 40.5 Product Dependencies
  1080
  - 40.5.1 I/O Lines
    1081
  - 40.5.2 Power Management
    1081
  - 40.5.3 Clocks
    1081
  - 40.5.4 DMA
    1081
  - 40.5.5 Interrupt
    1081
  - 40.5.6 Peripheral Events
    1081
- 40.6 Functional Description
  1081
  - 40.6.1 Capture Operation
    1081
  - 40.6.2 Peripheral DMA
    1082
  - 40.6.3 Peripheral Events
    1082
  - 40.6.4 Interrupt Generation
    1082
- 40.7 User Interface
  1084
  - 40.7.1 Configuration Register
    1085
  - 40.7.2 Control Register
    1087
  - 40.7.3 Interrupt Enable Register
    1088
  - 40.7.4 Interrupt Disable Register
    1089
  - 40.7.5 Interrupt Mask Register
    1090
  - 40.7.6 Status Register
    1091
  - 40.7.7 Interrupt Status Clear Register
    1092
  - 40.7.8 Receive Holding Register
    1093
  - 40.7.9 Version Register
    1094
- 40.8 Module Configuration
  1095
41. Cyclic Redundancy Check Calculation Unit (CRCCU)
1096
- 41.1 Features
  1096
- 41.2 Overview
  1096
- 41.3 Block Diagram
  1096
- 41.4 Product Dependencies
  1096
  - 41.4.1 Power Management
    1096
  - 41.4.2 Clocks
    1096
  - 41.4.3 Interrupts
    1096
  - 41.4.4 Debug Operation
    1096
- 41.5 Functional Description
  1097
- 41.6 User Interface
  1099
  - 41.6.1 Descriptor Base Address Register
    1100
  - 41.6.2 DMA Enable Register
    1101
  - 41.6.3 DMA Disable Register
    1102
  - 41.6.4 DMA Status Register
    1103
  - 41.6.5 DMA Interrupt Enable Register
    1104
  - 41.6.6 DMA Interrupt Disable Register
    1105
  - 41.6.7 DMA Interrupt Mask Register
    1106
  - 41.6.8 DMA Interrupt Status Register
    1107
  - 41.6.9 Control Register
    1108
  - 41.6.10 Mode Register
    1109
  - 41.6.11 Status Register
    1110
  - 41.6.12 Interrupt Enable Register
    1111
  - 41.6.13 Interrupt Disable Register
    1112
  - 41.6.14 Interrupt Mask Register
    1113
  - 41.6.15 Interrupt Status Register
    1114
  - 41.6.16 Version Register
    1115
  - 41.6.17 Transfer Address Register
    1116
  - 41.6.18 Transfer Control Register
    1117
  - 41.6.19 Transfer Reference Register
    1118
- 41.7 Module Configuration
  1119
42. Electrical Characteristics
1120
- 42.1 Absolute Maximum Ratings*
  1120
- 42.2 Operating Conditions
  1120
- 42.3 Supply Characteristics
  1120
- 42.4 Maximum Clock Frequencies
  1122
- 42.5 Power Consumption
  1124
- 42.6 I/O Pin Characteristics
  1135
- 42.7 Oscillator Characteristics
  1142
- 42.8 Flash Characteristics
  1148
- 42.9 Analog Characteristics
  1150
- 42.10 Timing Characteristics
  1161
  - 42.10.1 RESET_N Timing
    1161
  - 42.10.2 USART in SPI Mode Timing
    1161
    - 42.10.2.1 Master mode
      1161
    - 42.10.2.2 Slave mode
      1163
  - 42.10.3 SPI Timing
    1167
    - 42.10.3.1 Master mode
      1167
    - 42.10.3.2 Slave mode
      1168
  - 42.10.4 TWIM/TWIS Timing
    1170
  - 42.10.5 JTAG Timing
    1171
  - 42.10.6 SWD Timing
    1172
43. Mechanical Characteristics
1174
- 43.1 Thermal Considerations
  1174
  - 43.1.1 Thermal Data
    1174
  - 43.1.2 Junction Temperature
    1174
- 43.2 Package Drawings
  1175
- 43.3 Soldering Profile
  1184
44. Ordering Information
1185
45. Errata
1188
- 45.1 ATSAM4L4 /2 Rev. B & ATSAM4L8 Rev. A
  1188
  - 45.1.1 General
    1188
  - 45.1.2 SCIF
    1188
  - 45.1.3 WDT
    1188
  - 45.1.4 SPI
    1188
  - 45.1.5 TC
    1189
  - 45.1.6 USBC
    1189
  - 45.1.7 FLASHCALW
    1190
46. Datasheet Revision History
1191
- 46.1 Rev. A – 09/12
  1191
- 46.2 Rev. B – 10/12
  1191
- 46.3 Rev. C – 02/13
  1191
- 46.4 Rev. D – 03/13
  1191
- 46.5 Rev. E – 07/13
  1192
Table of Contents
1193

数据表 (ATSAM4L-XSTK)

文件大小：

13.4 MB
页数：

1204
Language:

English

打开用户手册

数据表 (ATSAM4L-XSTK)

数据表 (ATSAM4L-XSTK)

文件大小：

302.3 KB
页数：

2
Language:

English

打开用户手册