用户手册目录1. Abstract92. Overview93. Processor Version Register (PVR)94. General Parameters105. Design Enhancements for PowerPC 970MP105.1 Dual Core Design105.1.1 1MB L2 Cache per Core125.2 Processor Interconnect Bus135.2.1 SCOM control and status registers135.2.2 Test Modes135.2.2.1 Transmitter Pseudo-Random Data Test (RDT)135.2.2.2 Transmitter Electrical Shorts Test (EST)135.2.2.3 Receiver Electrical Shorts Test (REST)145.2.2.4 Receiver Random Data Self Test155.2.3 Bus Configuration155.3 PowerTuning175.3.1 Power Modes175.3.2 Time Base and Decrementer185.4 I2C Bus Interface185.4.1 Clock Dithering (New feature for 970FX DD3.0, enhanced in 970MP)185.4.2 Programmable Delays for Power Saving Mode Transitions195.5 Additional Dynamic Power Management195.6 More Precise Kelvin Circuitry197. Timings208. Package208.1 Design Considerations for a 970MP Thermal Solution208.1.1 Die Size208.1.2 Capacitor Position218.2 Description of Signal Changes218.3 PowerPC 970MP Microprocessor Package Dimensions22Revision Log25Dual Cores sharing processor interface11970MP Power Modes17PowerPC 970MP Mechanical Package (Side and Top View)23PowerPC 970MP Bottom Surface of CBGA Package (Bottom View)24PowerPC 970FX and 970MP Processor Version Registers (PVR)9General Parameters of the PowerPC 970FX and 970MP10PowerPC 970MP Programmable Delay Parameters16Power Mode States18PowerPC 970MP Latency of Deep Nap to Run Transition (Full Frequency Cycles)19PowerPC 970FX, and 970MP Die Size and Dimensions20970FX Pins Duplicated for each 970MP Processing Unit21New 970MP Pins21Deleted 970FX Pins - not found on 970MP22文件大小： 363.8 KB页数： 25Language: English打开用户手册
