用户手册目录RES0What is the 8088?18088 Pipelined Architecture1Efficient Program Coding1iAPX 88 Megabyte Memory Addressing1The 8088's 16-Bit Instruction Set1Interfacing the 80881Processor Extensions1Review1The iAPX 188 CPU1Benchmark Report: Intel® iAPX 88 vs. Zilog Z801Microcomputer Block Diagram18088 CPU1Program Execution in Standard Microprocessor1Pipelined Internal Architecture1Parallel Operation in 8088 CPU18088 Register Set1Data Group Registers1Base and Index Registers1Control Registers1iAPX 88 Architecture Quick Access to Four Segment Types1How an Address is Built1Process Relocation1iAPX 88 Addressing Modes1Four-Component Addressing Example1Data Transfer Instructions1Arithmetic Instructions1Bit Manipulation Instructions1String Instructions1Program Transfer Instructions1Processor Control Instructions18088 Bus Interface is Similar to 80851Multiplexed Bus Components for Low Chip-Count Applications1iAPX 88 Bipolar Support Components1iAPX 88 Longer Memory Access Time1iAPX 88 Processor Extensions1iAPX8811-,1iAPX 88 Architecture2Register Structure2Addressing Modes2Organization of Instruction Set2Assembly Language Programming2Instruction Set2How to Address One Million Bytes28088 Register Structure2Implicit Use of General Registers2Defining Bits in Instructions with One and Two Operands -:2Determing First Operand2Effective Addresses Used with Different Data Structures28088 Address Components2Reserved and Dedicated Memory Locations2Interrupt Vector Table in Memory2Effective Address Calculation Time2Translation Process2Assemblers and Compilers2Delimiters in ASM-8621 Architecture Features2CPU Pin Fu nctions38088 Bus Timing and Minimum Mode Status3Bus Interface3Memory and Peripheral Interface3Clock Generation3Reset3Ready Implementation and Timing3Interrupts3Bus Control Transfer3Maximum Mode Systems38088 CPU Pins3Time Multiplexing of Address and Data3Decoding of Status Signals S3-S63iAPX 88 Multiplexed Bus System3iAPX 88 With Buffered Demultiplexed Busses3iAPX 88 Basic Machine Cycle3iAPX 88 Compatible Multiplexed Bus Components3Multiplexed Bus Connections3DemultiplexedBusConnections3iAPX 88 With Buffered Demultiplexed Busses3How 16-bit Data is Arranged in 8-bit Memory3Generating Clock Signal With 8284A3CPU State Following Reset3iAPX 88 Bus Condition During Reset3iAPX 88 Bus During Reset38284A Reset Circuit3Constant Current on Reset Circuit3Normally READY Wait State Timing3Normally Not READY Wait State Timing3Using ROY 1/RDY 2 to Generate READy3Using AEN1/AEN2 to Generate READY3Single Wait State Generator3Interrupt Acknowledge Sequence3Interrupt Vector Table in Memory3Interrupt Priorities3iAPX 88 Bus Condition During HOLD3iAPX 88 and 8237A Connections3HOLD/HLDA Timing3iAPX 88 Using Maximum Mode3Min.lMax. Mode Pin Assignments3Request Grant Sequence Time (Max. Mode Only)3iAPX 88/21 Configuration3Zilog Z803Multiplexed System4iAPX 88 Demultiplexed System4iAPX 88-Based S100 Bus System4iAPX 88-Based CRT Controller4iAPX 88 Multiprocessing Systems4iAPX 88 Multiplexed System Design Example4iAPX 88 Demo Board Address Map4Vest Pocket Computer Component Layout4Vest Pocket Schematic4iAPX 88 Demultiplexed Bus System42114 Chip Select Connection4iAPX 88 S100 Bus System4iAPX 88 S100 Schematic4CRT Controller Block Diagram48276 Row Buffer Loading4Escape Character Recognition Code4iAPX 88 Multiprocessing System4Typical iAPX 88 Local Mode Configuration4Typical 8089 Remote Mode Configuration4iAPX 86,88 Multiprocessing System42 Execution Times iAPX 88 vs. Z80A53 Execution Times iAPX 88 vs. Z80B64 Execution Times with Comparable Memory Access65 Execution Times with Comparable Memory Access77 Memory Utilization (Bytes)8Table 7. Memory Utilization8Block Translate Flowchart14Bubble Sort'17Benchmark Report: Intel® iAPX 88 vs. Motorola MC680920iAPX 88 VS. Motorola MC68D9201 Architecture Features212 Execution Times (5 MHz 88/10 vs. 2 MHz 6809)24RESULTS243 Execution Times with "Equal" Memory Access Times25Table 4. Memory Utilization25CONCLUSION27Block Move Flowchart31Character Search Flowchart34iAPX 88/10 16-Bit HMOS Microprocessor378284A Clock Generator and Driver for iAPX 88/10, iAPX 88/10 Processors648282/8283 Octal Latch728286/8287 Octal Bus Transceiver77文件大小： 17.5 MB页数： 354Language: English打开用户手册
