用户手册 — Intel Xeon 7130N

目录

• 1 Introduction

  11
  • 1.1 Terminology

    12
  • 1.2 Reference Documents

    14
  • 1.3 State of Data

    14
• 2 Electrical Specifications

  15
  • 2.1 Front Side Bus and GTLREF

    15
    • 2.1.1 Front Side Bus Clock and Processor Clocking

      15
    • 2.1.2 Front Side Bus Clock Select (BSEL[1:0])

      16
    • 2.1.3 Phase Lock Loop (PLL) Power and Filter

      17
  • 2.2 Voltage Identification (VID)

    17
  • 2.3 Reserved, Unused, and TESTHI Pins

    20
  • 2.4 Mixing Processors

    20
  • 2.5 Front Side Bus Signal Groups

    21
  • 2.6 GTL+ Asynchronous Signals and AGTL + Asynchronous Signals

    22
  • 2.7 Test Access Port (TAP) Connection

    23
  • 2.8 Absolute Maximum and Minimum Ratings

    23
  • 2.9 Processor DC Specifications

    24
    • 2.9.1 Flexible Motherboard (FMB) Guidelines

      24
    • 2.9.2 Vcc Overshoot Specification

      28
• 3 Mechanical Specifications

  33
  • 3.1 Package Mechanical Drawing

    33
  • 3.2 Processor Component Keepout Zones

    36
  • 3.3 Package Loading Specifications

    36
  • 3.4 Package Handling Guidelines

    37
  • 3.5 Package Insertion Specifications

    37
  • 3.6 Processor Mass Specifications

    37
  • 3.7 Processor Materials

    37
  • 3.8 Processor Markings

    38
  • 3.9 Processor Pin-Out Coordinates

    39
• 4 Pin Listing

  41
  • 4.1 Dual-Core Intel Xeon Processor 7000 Series Pin Assignments

    41
    • 4.1.1 Pin Listing by Pin Name

      41
    • 4.1.2 Pin Listing by Pin Number

      50
• 5 Signal Definitions

  59
  • 5.1 Signal Definitions

    59
• 6 Thermal Specifications

  67
  • 6.1 Package Thermal Specifications

    67
    • 6.1.1 Thermal Specifications

      67
    • 6.1.2 Thermal Metrology

      70
  • 6.2 Processor Thermal Features

    70
    • 6.2.1 Thermal Monitor

      70
    • 6.2.2 On-Demand Mode

      71
    • 6.2.3 PROCHOT# Signal Pin

      71
    • 6.2.4 FORCEPR# Signal Pin

      72
    • 6.2.5 THERMTRIP# Signal Pin

      72
    • 6.2.6 Tcontrol and Fan Speed Reduction

      72
    • 6.2.7 Thermal Diode

      72
• 7 Features

  73
  • 7.1 Power-On Configuration Options

    73
  • 7.2 Clock Control and Low Power States

    73
    • 7.2.1 Normal State

      73
    • 7.2.2 HALT Power Down State

      74
    • 7.2.3 Stop-Grant State

      74
    • 7.2.4 HALT/Grant Snoop State

      75
    • 7.2.5 Enhanced HALT Powerdown State

      75
  • 7.3 Enhanced Intel SpeedStep® Technology

    76
  • 7.4 System Management Bus (SMBus) Interface

    76
    • 7.4.1 Processor Information ROM (PIROM)

      77
    • 7.4.2 Scratch EEPROM

      80
    • 7.4.3 PIROM and Scratch EEPROM Supported SMBus Transactions

      80
    • 7.4.4 SMBus Thermal Sensor

      81
    • 7.4.5 Thermal Sensor Supported SMBus Transactions

      81
    • 7.4.6 SMBus Thermal Sensor Registers

      84
    • 7.4.7 SMBus Thermal Sensor Alert Interrupt

      87
    • 7.4.8 SMBus Device Addressing

      88
    • 7.4.9 Managing Data in the PIROM

      89
• 8 Boxed Processor Specifications

  97
  • 8.1 Introduction

    97
  • 8.2 Mechanical Specifications

    98
    • 8.2.1 Boxed Processor Heatsink Dimensions

      98
    • 8.2.2 Boxed Processor Heatsink Weight

      104
    • 8.2.3 Boxed Processor Retention Mechanism and Heatsink Supports

      104
  • 8.3 Thermal Specifications

    105
    • 8.3.1 Boxed Processor Cooling Requirements

      105
    • 8.3.2 Boxed Processor Contents

      105
• 9 Debug Tools Specifications

  107
  • 9.1 Logic Analyzer Interface (LAI)

    107
    • 9.1.1 Mechanical Considerations

      107
    • 9.1.2 Electrical Considerations

      107