用户手册 — Renesas H8S/2111B

目录

• Cover

  1
• Keep safety first in your circuit designs!

  3
• Notes regarding these materials

  3
• General Precautions on Handling of Product

  4
• Configuration of This Manual

  5
• Preface

  6
• Contents

  9
• Figures

  23
• Tables

  31
• Section 1 Overview

  35
  • 1.1 Features

    35
  • 1.2 Internal Block Diagram

    36
  • 1.3 Pin Description

    37
    • 1.3.1 Pin Arrangement

      37
    • 1.3.2 Pin Functions in Each Operating Mode

      38
    • 1.3.3 Pin Functions

      43
• Section 2 CPU

  47
  • 2.1 Features

    47
    • 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU

      48
    • 2.1.2 Differences from H8/300 CPU

      49
    • 2.1.3 Differences from H8/300H CPU

      49
  • 2.2 CPU Operating Modes

    50
    • 2.2.1 Normal Mode

      50
    • 2.2.2 Advanced Mode

      52
  • 2.3 Address Space

    54
  • 2.4 Register Configuration

    55
    • 2.4.1 General Registers

      56
    • 2.4.2 Program Counter (PC)

      57
    • 2.4.3 Extended Control Register (EXR)

      57
    • 2.4.4 Condition-Code Register (CCR)

      58
    • 2.4.5 Initial Register Values

      59
  • 2.5 Data Formats

    60
    • 2.5.1 General Register Data Formats

      60
    • 2.5.2 Memory Data Formats

      62
  • 2.6 Instruction Set

    63
    • 2.6.1 Table of Instructions Classified by Function

      64
    • 2.6.2 Basic Instruction Formats

      73
  • 2.7 Addressing Modes and Effective Address Calculation

    74
    • 2.7.1 Register Direct—Rn

      74
    • 2.7.2 Register Indirect—@ERn

      74
    • 2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)

      75
    • 2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn

      75
    • 2.7.5 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32

      75
    • 2.7.6 Immediate—#xx:8, #xx:16, or #xx:32

      76
    • 2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC)

      76
    • 2.7.8 Memory Indirect—@@aa:8

      77
    • 2.7.9 Effective Address Calculation

      78
  • 2.8 Processing States

    80
  • 2.9 Usage Notes

    82
    • 2.9.1 Note on TAS Instruction Usage

      82
    • 2.9.2 Note on STM/LDM Instruction Usage

      82
    • 2.9.3 Note on Bit Manipulation Instructions

      82
    • 2.9.4 EEPMOV Instruction

      83
• Section 3 MCU Operating Modes

  85
  • 3.1 MCU Operating Mode Selection

    85
  • 3.2 Register Descriptions

    86
    • 3.2.1 Mode Control Register (MDCR)

      86
    • 3.2.2 System Control Register (SYSCR)

      87
    • 3.2.3 Serial Timer Control Register (STCR)

      89
  • 3.3 Operating Mode Descriptions

    90
    • 3.3.1 Mode 2

      90
    • 3.3.2 Mode 3

      90
  • 3.4 Address Map

    91
• Section 4 Exception Handling

  93
  • 4.1 Exception Handling Types and Priority

    93
  • 4.2 Exception Sources and Exception Vector Table

    94
  • 4.3 Reset

    95
    • 4.3.1 Reset Exception Handling

      95
    • 4.3.2 Interrupts after Reset

      96
    • 4.3.3 On-Chip Peripheral Modules after Reset is Cancelled

      96
  • 4.4 Interrupt Exception Handling

    97
  • 4.5 Trap Instruction Exception Handling

    97
  • 4.6 Stack Status after Exception Handling

    98
  • 4.7 Usage Note

    99
• Section 5 Interrupt Controller

  101
  • 5.1 Features

    101
  • 5.2 Input/Output Pins

    102
  • 5.3 Register Descriptions

    103
    • 5.3.1 Interrupt Control Registers A to C (ICRA to ICRC)

      103
    • 5.3.2 Address Break Control Register (ABRKCR)

      104
    • 5.3.3 Break Address Registers A to C (BARA to BARC)

      105
    • 5.3.4 IRQ Sense Control Registers (ISCRH, ISCRL)

      106
    • 5.3.5 IRQ Enable Register (IER)

      107
    • 5.3.6 IRQ Status Register (ISR)

      107
    • 5.3.7 Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR) Wake-Up Event Interrupt Mask Register (WUEMRB)

      107
  • 5.4 Interrupt Sources

    110
    • 5.4.1 External Interrupts

      110
    • 5.4.2 Internal Interrupts

      111
  • 5.5 Interrupt Exception Handling Vector Table

    112
  • 5.6 Interrupt Control Modes and Interrupt Operation

    114
    • 5.6.1 Interrupt Control Mode 0

      114
    • 5.6.2 Interrupt Control Mode 1

      116
    • 5.6.3 Interrupt Exception Handling Sequence

      119
    • 5.6.4 Interrupt Response Times

      120
  • 5.7 Address Break

    121
    • 5.7.1 Features

      121
    • 5.7.2 Block Diagram

      121
    • 5.7.3 Operation

      122
    • 5.7.4 Usage Notes

      122
  • 5.8 Usage Notes

    124
    • 5.8.1 Conflict between Interrupt Generation and Disabling

      124
    • 5.8.2 Instructions that Disable Interrupts

      125
    • 5.8.3 Interrupts during Execution of EEPMOV Instruction

      125
    • 5.8.4 IRQ Status Register (ISR)

      125
• Section 6 Bus Controller (BSC)

  127
  • 6.1 Register Descriptions

    127
    • 6.1.1 Bus Control Register (BCR)

      127
    • 6.1.2 Wait State Control Register (WSCR)

      128
• Section 7 I/O Ports

  129
  • 7.1 Port 1

    134
    • 7.1.1 Port 1 Data Direction Register (P1DDR)

      134
    • 7.1.2 Port 1 Data Register (P1DR)

      134
    • 7.1.3 Port 1 Pull-Up MOS Control Register (P1PCR)

      135
    • 7.1.4 Pin Functions

      135
    • 7.1.5 Port 1 Input Pull-Up MOS

      136
  • 7.2 Port 2

    136
    • 7.2.1 Port 2 Data Direction Register (P2DDR)

      136
    • 7.2.2 Port 2 Data Register (P2DR))

      137
    • 7.2.3 Port 2 Pull-Up MOS Control Register (P2PCR)

      137
    • 7.2.4 Pin Functions

      137
    • 7.2.5 Port 2 Input Pull-Up MOS

      138
  • 7.3 Port 3

    138
    • 7.3.1 Port 3 Data Direction Register (P3DDR)

      138
    • 7.3.2 Port 3 Data Register (P3DR)

      139
    • 7.3.3 Port 3 Pull-Up MOS Control Register (P3PCR)

      139
    • 7.3.4 Pin Functions

      140
    • 7.3.5 Port 3 Input Pull-Up MOS

      140
  • 7.4 Port 4

    141
    • 7.4.1 Port 4 Data Direction Register (P4DDR)

      141
    • 7.4.2 Port 4 Data Register (P4DR)

      141
    • 7.4.3 Pin Functions

      142
  • 7.5 Port 5

    144
    • 7.5.1 Port 5 Data Direction Register (P5DDR)

      144
    • 7.5.2 Port 5 Data Register (P5DR)

      144
    • 7.5.3 Pin Functions

      145
  • 7.6 Port 6

    146
    • 7.6.1 Port 6 Data Direction Register (P6DDR)

      146
    • 7.6.2 Port 6 Data Register (P6DR)

      147
    • 7.6.3 Port 6 Pull-Up MOS Control Register (KMPCR)

      147
    • 7.6.4 System Control Register 2 (SYSCR2)

      148
    • 7.6.5 Pin Functions

      148
    • 7.6.6 Port 6 Input Pull-Up MOS

      150
  • 7.7 Port 7

    151
    • 7.7.1 Port 7 Input Data Register (P7PIN)

      151
    • 7.7.2 Pin Functions

      151
  • 7.8 Port 8

    152
    • 7.8.1 Port 8 Data Direction Register (P8DDR)

      152
    • 7.8.2 Port 8 Data Register (P8DR)

      152
    • 7.8.3 Pin Functions

      153
  • 7.9 Port 9

    156
    • 7.9.1 Port 9 Data Direction Register (P9DDR)

      156
    • 7.9.2 Port 9 Data Register (P9DR)

      156
    • 7.9.3 Pin Functions

      157
  • 7.10 Port A

    159
    • 7.10.1 Port A Data Direction Register (PADDR)

      159
    • 7.10.2 Port A Output Data Register (PAODR)

      159
    • 7.10.3 Port A Input Data Register (PAPIN)

      160
    • 7.10.4 Pin Functions

      160
    • 7.10.5 Port A Input Pull-Up MOS

      162
  • 7.11 Port B

    163
    • 7.11.1 Port B Data Direction Register (PBDDR)

      163
    • 7.11.2 Port B Output Data Register (PBODR)

      163
    • 7.11.3 Port B Input Data Register (PBPIN)

      164
    • 7.11.4 Pin Functions

      164
    • 7.11.5 Port B Input Pull-Up MOS

      165
  • 7.12 Ports C, D

    166
    • 7.12.1 Port C and Port D Data Direction Registers (PCDDR, PDDDR)

      166
    • 7.12.2 Port C and Port D Output Data Registers (PCODR, PDODR)

      167
    • 7.12.3 Port C and Port D Input Data Registers (PCPIN, PDPIN)

      167
    • 7.12.4 Port C and Port D Nch-OD Control Register (PCNOCR, PDNOCR)

      168
    • 7.12.5 Pin Functions

      169
    • 7.12.6 Input Pull-Up MOS in Ports C and D

      169
  • 7.13 Ports E, F

    170
    • 7.13.1 Port E and Port F Data Direction Registers (PEDDR, PFDDR)

      170
    • 7.13.2 Port E and Port F Output Data Registers (PEODR, PFODR)

      171
    • 7.13.3 Port E and Port F Input Data Registers (PEPIN, PFPIN)

      172
    • 7.13.4 Pin Functions

      172
    • 7.13.5 Port E and Port F Nch-OD Control Register (PENOCR, PFNOCR)

      174
    • 7.13.6 Pin Functions

      175
    • 7.13.7 Input Pull-Up MOS in Ports E and F

      175
  • 7.14 Port G

    176
    • 7.14.1 Port G Data Direction Register (PGDDR)

      176
    • 7.14.2 Port G Output Data Register (PGODR)

      177
    • 7.14.3 Port G Input Data Register (PGPIN)

      177
    • 7.14.4 Pin Functions

      178
    • 7.14.5 Port G Nch-OD Control Register (PGNOCR)

      179
    • 7.14.6 Pin Functions

      179
• Section 8 8-Bit PWM Timer (PWM)

  181
  • 8.1 Features

    181
  • 8.2 Input/Output Pins

    182
  • 8.3 Register Descriptions

    182
    • 8.3.1 PWM Register Select (PWSL)

      183
    • 8.3.2 PWM Data Registers 7 to 0 (PWDR7 to PWD0)

      185
    • 8.3.3 PWM Data Polarity Register A (PWDPRA)

      185
    • 8.3.4 PWM Output Enable Register A (PWOERA)

      186
    • 8.3.5 Peripheral Clock Select Register (PCSR)

      186
  • 8.4 Operation

    187
    • 8.4.1 PWM Setting Example

      189
    • 8.4.2 Diagram of PWM Used as D/A Converter

      189
  • 8.5 Usage Notes

    190
    • 8.5.1 Module Stop Mode Setting

      190
• Section 9 16-Bit Free-Running Timer (FRT)

  191
  • 9.1 Features

    191
  • 9.2 Input/Output Pins

    193
  • 9.3 Register Descriptions

    193
    • 9.3.1 Free-Running Counter (FRC)

      194
    • 9.3.2 Output Compare Registers A and B (OCRA, OCRB)

      194
    • 9.3.3 Input Capture Registers A to D (ICRA to ICRD)

      194
    • 9.3.4 Output Compare Registers AR and AF (OCRAR, OCRAF)

      195
    • 9.3.5 Output Compare Register DM (OCRDM)

      195
    • 9.3.6 Timer Interrupt Enable Register (TIER)

      196
    • 9.3.7 Timer Control/Status Register (TCSR)

      197
    • 9.3.8 Timer Control Register (TCR)

      200
    • 9.3.9 Timer Output Compare Control Register (TOCR)

      201
  • 9.4 Operation

    203
    • 9.4.1 Pulse Output

      203
  • 9.5 Operation Timing

    204
    • 9.5.1 FRC Increment Timing

      204
    • 9.5.2 Output Compare Output Timing

      205
    • 9.5.3 FRC Clear Timing

      205
    • 9.5.4 Input Capture Input Timing

      206
    • 9.5.5 Buffered Input Capture Input Timing

      207
    • 9.5.6 Timing of Input Capture Flag (ICF) Setting

      208
    • 9.5.7 Timing of Output Compare Flag (OCF) setting

      208
    • 9.5.8 Timing of FRC Overflow Flag Setting

      209
    • 9.5.9 Automatic Addition Timing

      209
    • 9.5.10 Mask Signal Generation Timing

      210
  • 9.6 Interrupt Sources

    211
  • 9.7 Usage Notes

    211
    • 9.7.1 Conflict between FRC Write and Clear

      211
    • 9.7.2 Conflict between FRC Write and Increment

      212
    • 9.7.3 Conflict between OCR Write and Compare-Match

      212
    • 9.7.4 Switching of Internal Clock and FRC Operation

      214
    • 9.7.5 Module Stop Mode Setting

      215
• Section 10 8-Bit Timer (TMR)

  217
  • 10.1 Features

    217
  • 10.2 Input/Output Pins

    222
  • 10.3 Register Descriptions

    223
    • 10.3.1 Timer Counter (TCNT)

      225
    • 10.3.2 Time Constant Register A (TCORA)

      225
    • 10.3.3 Time Constant Register B (TCORB)

      225
    • 10.3.4 Timer Control Register (TCR)

      226
    • 10.3.5 Timer Control/Status Register (TCSR)

      230
    • 10.3.6 Time Constant Register (TCORC)

      236
    • 10.3.7 Input Capture Registers R and F (TICRR, TICRF, TICRR_A and TICRF_A)

      236
    • 10.3.8 Timer Input Select Register (TISR and TISR_B)

      236
    • 10.3.9 Timer Connection Register I (TCONRI)

      237
    • 10.3.10 Timer Connection Register S (TCONRS)

      237
    • 10.3.11 Timer XY Control Register (TCRXY)

      238
    • 10.3.12 Timer AB Control Register (TCRAB)

      239
  • 10.4 Operation

    240
    • 10.4.1 Pulse Output

      240
  • 10.5 Operation Timing

    241
    • 10.5.1 TCNT Count Timing

      241
    • 10.5.2 Timing of CMFA and CMFB Setting at Compare-Match

      241
    • 10.5.3 Timing of Timer Output at Compare-Match

      242
    • 10.5.4 Timing of Counter Clear at Compare-Match

      242
    • 10.5.5 TCNT External Reset Timing

      243
    • 10.5.6 Timing of Overflow Flag (OVF) Setting

      243
  • 10.6 TMR_0 and TMR_1 Cascaded Connection

    244
    • 10.6.1 16-Bit Count Mode

      244
    • 10.6.2 Compare-Match Count Mode

      244
  • 10.7 TMR_Y and TMR_X Cascaded Connection

    245
    • 10.7.1 16-Bit Count Mode

      245
    • 10.7.2 Compare-Match Count Mode

      245
    • 10.7.3 Input Capture Operation

      246
  • 10.8 TMR_B and TMR_A Cascaded Connection

    246
    • 10.8.1 16-Bit Count Mode

      246
    • 10.8.2 Compare-Match Count Mode

      246
    • 10.8.3 Input Capture Operation

      247
  • 10.9 Interrupt Sources

    249
  • 10.10 Usage Notes

    250
    • 10.10.1 Conflict between TCNT Write and Counter Clear

      250
    • 10.10.2 Conflict between TCNT Write and Count-Up

      250
    • 10.10.3 Conflict between TCOR Write and Compare-Match

      251
    • 10.10.4 Conflict between Compare-Matches A and B

      251
    • 10.10.5 Switching of Internal Clocks and TCNT Operation

      252
    • 10.10.6 Mode Setting with Cascaded Connection

      253
    • 10.10.7 Module Stop Mode Setting

      253
• Section 11 Watchdog Timer (WDT)

  255
  • 11.1 Features

    255
  • 11.2 Input/Output Pins

    257
  • 11.3 Register Descriptions

    257
    • 11.3.1 Timer Counter (TCNT)

      257
    • 11.3.2 Timer Control/Status Register (TCSR)

      258
  • 11.4 Operation

    261
    • 11.4.1 Watchdog Timer Mode

      261
    • 11.4.2 Interval Timer Mode

      263
    • 11.4.3 RESO Signal Output Timing

      264
  • 11.5 Interrupt Sources

    264
  • 11.6 Usage Notes

    265
    • 11.6.1 Notes on Register Access

      265
    • 11.6.2 Conflict between Timer Counter (TCNT) Write and Increment

      266
    • 11.6.3 Changing Values of CKS2 to CKS0 Bits

      266
    • 11.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode

      266
    • 11.6.5 System Reset by RESO Signal

      267
    • 11.6.6 Counter Values during Transitions between High-Speed, Sub-Active, and Watch Modes

      267
• Section 12 Serial Communication Interface (SCI)

  269
  • 12.1 Features

    269
  • 12.2 Input/Output Pins

    270
  • 12.3 Register Descriptions

    271
    • 12.3.1 Receive Shift Register (RSR)

      271
    • 12.3.2 Receive Data Register (RDR)

      271
    • 12.3.3 Transmit Data Register (TDR)

      271
    • 12.3.4 Transmit Shift Register (TSR)

      272
    • 12.3.5 Serial Mode Register (SMR)

      272
    • 12.3.6 Serial Control Register (SCR)

      273
    • 12.3.7 Serial Status Register (SSR)

      275
    • 12.3.8 Serial Interface Mode Register (SCMR)

      277
    • 12.3.9 Bit Rate Register (BRR)

      278
    • 12.3.10 Serial Pin Select Register (SPSR)

      283
  • 12.4 Operation in Asynchronous Mode

    283
    • 12.4.1 Data Transfer Format

      284
    • 12.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode

      285
    • 12.4.3 Clock

      286
    • 12.4.4 SCI Initialization (Asynchronous Mode)

      287
    • 12.4.5 Data Transmission (Asynchronous Mode)

      288
    • 12.4.6 Serial Data Reception (Asynchronous Mode)

      290
  • 12.5 Multiprocessor Communication Function

    293
    • 12.5.1 Multiprocessor Serial Data Transmission

      294
    • 12.5.2 Multiprocessor Serial Data Reception

      295
  • 12.6 Operation in Clocked Synchronous Mode

    298
    • 12.6.1 Clock

      298
    • 12.6.2 SCI Initialization (Clocked Synchronous Mode)

      299
    • 12.6.3 Serial Data Transmission (Clocked Synchronous Mode)

      300
    • 12.6.4 Serial Data Reception (Clocked Synchronous Mode)

      302
    • 12.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode)

      303
  • 12.7 Interrupt Sources

    305
  • 12.8 Usage Notes

    306
    • 12.8.1 Module Stop Mode Setting

      306
    • 12.8.2 Break Detection and Processing

      306
    • 12.8.3 Mark State and Break Detection

      306
    • 12.8.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)

      306
    • 12.8.5 Relation between Writing to TDR and TDRE Flag

      306
    • 12.8.6 SCI Operations during Mode Transitions

      307
    • 12.8.7 Switching from SCK Pins to Port Pins

      310
• Section 13 I2C Bus Interface (IIC)

  311
  • 13.1 Features

    311
  • 13.2 Input/Output Pins

    314
  • 13.3 Register Descriptions

    315
    • 13.3.1 I2C Bus Data Register (ICDR)

      316
    • 13.3.2 Slave Address Register (SAR)

      317
    • 13.3.3 Second Slave Address Register (SARX)

      318
    • 13.3.4 I2C Bus Mode Register (ICMR)

      320
    • 13.3.5 I2C Bus Control Register (ICCR)

      323
    • 13.3.6 I2C Bus Status Register (ICSR)

      331
    • 13.3.7 DDC Switch Register (DDCSWR)

      335
    • 13.3.8 I2C Bus Extended Control Register (ICXR)

      336
    • 13.3.9 Port G Control Register (PGCTL)

      340
  • 13.4 Operation

    341
    • 13.4.1 I2C Bus Data Format

      341
    • 13.4.2 Initialization

      343
    • 13.4.3 Master Transmit Operation

      343
    • 13.4.4 Master Receive Operation

      348
    • 13.4.5 Slave Receive Operation

      355
    • 13.4.6 Slave Transmit Operation

      362
    • 13.4.7 IRIC Setting Timing and SCL Control

      365
    • 13.4.8 Noise Canceller

      368
    • 13.4.9 Initialization of Internal State

      369
  • 13.5 Interrupt Sources

    370
  • 13.6 Usage Notes

    371
    • 13.6.1 Module Stop Mode Setting

      381
• Section 14 Keyboard Buffer Controller

  383
  • 14.1 Features

    383
  • 14.2 Input/Output Pins

    384
  • 14.3 Register Descriptions

    385
    • 14.3.1 Keyboard Control Register H (KBCRH)

      385
    • 14.3.2 Keyboard Control Register L (KBCRL)

      387
    • 14.3.3 Keyboard Data Buffer Register (KBBR)

      388
  • 14.4 Operation

    389
    • 14.4.1 Receive Operation

      389
    • 14.4.2 Transmit Operation

      390
    • 14.4.3 Receive Abort

      393
    • 14.4.4 KCLKI and KDI Read Timing

      395
    • 14.4.5 KCLKO and KDO Write Timing

      395
    • 14.4.6 KBF Setting Timing and KCLK Control

      396
    • 14.4.7 Receive Timing

      397
    • 14.4.8 KCLK Fall Interrupt Operation

      398
  • 14.5 Usage Notes

    399
    • 14.5.1 KBIOE Setting and KCLK Falling Edge Detection

      399
    • 14.5.2 Module Stop Mode Setting

      400
• Section 15 Host Interface (LPC)

  401
  • 15.1 Features

    401
  • 15.2 Input/Output Pins

    403
  • 15.3 Register Descriptions

    404
    • 15.3.1 Host Interface Control Registers 0 and 1 (HICR0, HICR1)

      405
    • 15.3.2 Host Interface Control Registers 2 and 3 (HICR2, HICR3)

      411
    • 15.3.3 LPC Channel 3 Address Register (LADR3)

      413
    • 15.3.4 Input Data Registers 1 to 3 (IDR1 to IDR3)

      414
    • 15.3.5 Output Data Registers 1 to 3 (ODR1 to ODR3)

      415
    • 15.3.6 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15)

      415
    • 15.3.7 Status Registers 1 to 3 (STR1 to STR3)

      415
    • 15.3.8 SERIRQ Control Registers 0 and 1 (SIRQCR0, SIRQCR1)

      421
    • 15.3.9 Host Interface Select Register (HISEL)

      429
  • 15.4 Operation

    430
    • 15.4.1 Host Interface Activation

      430
    • 15.4.2 LPC I/O Cycles

      431
    • 15.4.3 A20 Gate

      432
    • 15.4.4 Host Interface Shutdown Function (LPCPD)

      435
    • 15.4.5 Host Interface Serialized Interrupt Operation (SERIRQ)

      439
    • 15.4.6 Host Interface Clock Start Request (CLKRUN)

      441
  • 15.5 Interrupt Sources

    442
    • 15.5.1 IBFI1, IBFI2, IBFI3, and ERRI

      442
    • 15.5.2 SMI, HIRQ1, HIRQ6, HIRQ9, HIRQ10, HIRQ11, and HIRQ12

      442
  • 15.6 Usage Notes

    445
    • 15.6.1 Module Stop Mode Setting

      445
    • 15.6.2 Notes on Using Host Interface

      445
• Section 16 A/D Converter

  447
  • 16.1 Features

    447
  • 16.2 Input/Output Pins

    449
  • 16.3 Register Descriptions

    450
    • 16.3.1 A/D Data Registers A to D (ADDRA to ADDRD)

      450
    • 16.3.2 A/D Control/Status Register (ADCSR)

      451
    • 16.3.3 A/D Control Register (ADCR)

      452
  • 16.4 Operation

    453
    • 16.4.1 Single Mode

      453
    • 16.4.2 Scan Mode

      453
    • 16.4.3 Input Sampling and A/D Conversion Time

      455
    • 16.4.4 External Trigger Input Timing

      456
  • 16.5 Interrupt Sources

    457
  • 16.6 A/D Conversion Accuracy Definitions

    457
  • 16.7 Usage Notes

    459
    • 16.7.1 Permissible Signal Source Impedance

      459
    • 16.7.2 Influences on Absolute Accuracy

      459
    • 16.7.3 Setting Range of Analog Power Supply and Other Pins

      460
    • 16.7.4 Notes on Board Design

      460
    • 16.7.5 Notes on Noise Countermeasures

      460
    • 16.7.6 Module Stop Mode Setting

      461
• Section 17 RAM

  463
• Section 18 ROM

  465
  • 18.1 Features

    465
  • 18.2 Mode Transitions

    467
  • 18.3 Block Configuration

    470
  • 18.4 Input/Output Pins

    471
  • 18.5 Register Descriptions

    471
    • 18.5.1 Flash Memory Control Register 1 (FLMCR1)

      472
    • 18.5.2 Flash Memory Control Register 2 (FLMCR2)

      473
    • 18.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2)

      474
  • 18.6 Operating Modes

    475
  • 18.7 On-Board Programming Modes

    475
    • 18.7.1 Boot Mode

      476
    • 18.7.2 User Program Mode

      479
  • 18.8 Flash Memory Programming/Erasing

    480
    • 18.8.1 Program/Program-Verify

      480
    • 18.8.2 Erase/Erase-Verify

      482
  • 18.9 Program/Erase Protection

    484
    • 18.9.1 Hardware Protection

      484
    • 18.9.2 Software Protection

      484
    • 18.9.3 Error Protection

      484
  • 18.10 Interrupts during Flash Memory Programming/Erasing

    485
  • 18.11 Programmer Mode

    486
  • 18.12 Usage Notes

    487
• Section 19 Clock Pulse Generator

  489
  • 19.1 Oscillator

    490
    • 19.1.1 Connecting Crystal Resonator

      490
    • 19.1.2 External Clock Input Method

      491
  • 19.2 Duty Correction Circuit

    493
  • 19.3 Medium-Speed Clock Divider

    493
  • 19.4 Bus Master Clock Select Circuit

    493
  • 19.5 Subclock Input Circuit

    494
  • 19.6 Waveform Forming Circuit

    494
  • 19.7 Clock Select Circuit

    495
  • 19.8 Usage Notes

    495
    • 19.8.1 Note on Resonator

      495
    • 19.8.2 Notes on Board Design

      495
• Section 20 Power-Down Modes

  497
  • 20.1 Register Descriptions

    497
    • 20.1.1 Standby Control Register (SBYCR)

      498
    • 20.1.2 Low-Power Control Register (LPWRCR)

      499
    • 20.1.3 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL)

      501
  • 20.2 Mode Transitions and LSI States

    502
  • 20.3 Medium-Speed Mode

    504
  • 20.4 Sleep Mode

    505
  • 20.5 Software Standby Mode

    505
  • 20.6 Hardware Standby Mode

    507
  • 20.7 Watch Mode

    508
  • 20.8 Subsleep Mode

    509
  • 20.9 Subactive Mode

    510
  • 20.10 Module Stop Mode

    511
  • 20.11 Direct Transitions

    511
  • 20.12 Usage Notes

    512
    • 20.12.1 I/O Port Status

      512
    • 20.12.2 Current Consumption when Waiting for Oscillation Stabilization

      512
• Section 21 List of Registers

  513
  • 21.1 Register Addresses (Address Order)

    514
  • 21.2 Register Bits

    523
  • 21.3 Register States in Each Operating Mode

    531
  • 21.4 Register Select Conditions

    539
• Section 22 Electrical Characteristics

  547
  • 22.1 Absolute Maximum Ratings

    547
  • 22.2 DC Characteristics

    548
  • 22.3 AC Characteristics

    554
    • 22.3.1 Clock Timing

      555
    • 22.3.2 Control Signal Timing

      556
    • 22.3.3 Timing of On-Chip Peripheral Modules

      557
  • 22.4 A/D Conversion Characteristics

    560
  • 22.5 Flash Memory Characteristics

    561
  • 22.6 Usage Note

    563
  • 22.7 Timing Chart

    563
    • 22.7.1 Clock Timing

      563
    • 22.7.2 Control Signal Timing

      565
    • 22.7.3 On-Chip Peripheral Module Timing

      566
• Appendix

  571
  • A. I/O Port States in Each Processing State

    571
  • B. Product Codes

    572
  • C. Package Dimensions

    573
• Index

  575
• Colphon

  579
• Address List

  580
• Back Cover

  582