用户手册目录Introduction9Applications of the ERTEC 2009Features of the ERTEC 2009Structure of the ERTEC 20010ERTEC 200 Package11Signal Function Description12GPIO 0 to 31 and Alternative Functions12JTAG and Debug13Trace Port13Clock and Reset14Test Pins14EMIF (External Memory Interface)14LBU, MII Interface or ETM Trace Interface16Ethernet PHY1 and PHY218Power Supply19UARM946E-S Processor21Structure of ARM946E-S21Description of ARM946E-S22Operating Frequency of ARM946E-S22Cache Structure of ARM946E-S22Tightly Coupled Memory (TCM)22Memory Protection Unit (MPU)23Bus Interface of ARM946E-S23ARM946E-S Embedded Trace Macrocell (ETM9)23ARM Interrupt Controller (ICU)23Prioritization of Interrupts24Trigger Modes24Masking the Interrupt Inputs24Software Interrupts for IRQ24Nested Interrupt Structure24EOI End-Of-Interrupt24IRQ Interrupt Sources25FIQ Interrupt Sources25IRQ Interrupts as FIQ Interrupt Sources26Interrupt Control Register26ICU Register Description27ARM946E-S Register31Bus System of the ERTEC 20032“Multilayer AHB” Communication Bus32AHB Arbiter32AHB Master-Slave Coupling32APB I/O Bus32I/O on APB bus33BOOT ROM33Booting from External ROM34Booting via SPI34Booting via UART34Booting via LBU34Memory Swapping34General Purpose I/O (GPIO)35Address Assignment of GPIO Registers36GPIO Register Description36Timer 0/1/238Timer 0 and Timer 138Timer 0/1 Interrupts39Timer 0/1 Prescaler39Cascading of Timers 0/139Timer 239Address Assignment of Timer Registers40Timer Register Description40F-Timer Function43Address Assignment of F-Timer Registers44F-Timer Register Description44Watchdog Timers45Watchdog Timer 045Watchdog Timer 145Watchdog Interrupt45WDOUT0_N45WDOUT1_N45Watchdog Registers46Address Assignment of Watchdog Registers46Watchdog Register Description46UART Interface48Address Assignment of UART Registers49UART Register Description50Synchronous Interface SPI54Address Assignment of SPI Register55SPI Register Description56System control register58Address Assignment of System Control Registers58System Control Register Description59General Hardware Functions64Clock Generation and Clock Supply64Clock Supply in ERTEC 20064JTAG Clock Supply65Clock Supply for PHYs and Ethernet MACs65Reset Logic of the ERTEC 20065PowerOn reset65Hardware Reset66Watchdog Reset66Software reset66IRT Switch Reset66Address Space and Timeout Monitoring67AHB Bus Monitoring67APB Bus Monitoring67EMIF Monitoring67Configuration Options on the ERTEC 20067External Memory Interface (EMIF)69Address Assignment of EMIF Registers70EMIF Register Description70Local Bus Unit (LBU).74Page Range Setting76Page Offset Setting76LBU Address Mapping77Page Control Setting78Host Access to the ERTEC20078LBU Read from ERTEC 200 with separate Read/Write line (LBU_R79LBU Write to ERTEC 200 with separate Read/Write line (LBU_RD80LBU Read from ERTEC 200 with common Read/Write line (LBU_RDY81LBU Write to ERTEC 200 with common Read/Write line (LBU_RDY_82Host Interrupt Handling:82Address Assignment of LBU Registers83LBU Register Description83DMA-Controller85DMA Register Address Assignment86Description of DMA Registers86Multiport Ethernet PHY88Memory Description91Memory Partitioning of the ERTEC 20091Detailed Memory Description92Test and Debugging94ETM9 Embedded Trace Macrocell94Trace Modes94Features of the ETM9 Module94ETM9 Registers94Trace Interface95JTAG Interface95Debugging via UART95Miscellaneous96Acronyms/Glossary:96References:97文件大小: 1.9 MB页数: 97Language: English打开用户手册