Renesas rl78 Benutzerhandbuch
RL78/G1A
CHAPTER 13 SERIAL INTERFACE IICA
Figure 13-9. Format of IICA Control Register 01 (IICCTL01) (2/2)
CLD0
Detection of SCLA0 pin level (valid only when IICE0 = 1)
0
The SCLA0 pin was detected at low level.
1
The SCLA0 pin was detected at high level.
Condition for clearing (CLD0 = 0)
Condition for setting (CLD0 = 1)
• When the SCLA0 pin is at low level
• When the SCLA0 pin is at high level
• When IICE0 = 0 (operation stop)
• Reset
• Reset
DAD0
Detection of SDAA0 pin level (valid only when IICE0 = 1)
0
The SDAA0 pin was detected at low level.
1
The SDAA0 pin was detected at high level.
Condition for clearing (DAD0 = 0)
Condition for setting (DAD0 = 1)
• When the SDAA0 pin is at low level
• When the SDAA0 pin is at high level
• When IICE0 = 0 (operation stop)
• Reset
• Reset
SMC0 Operation
mode
switching
0
Operates in standard mode (fastest transfer rate: 100 kbps).
1
Operates in fast mode (fastest transfer rate: 400 kbps) or fast mode plus (fastest transfer rate: 1
Mbps).
DFC0
Digital filter operation control
0
Digital filter off.
1
Digital filter on.
Use the digital filter only in fast mode and fast mode plus.
The digital filter is used for noise elimination.
The transfer clock does not vary, regardless of the DFC0 bit being set (1) or cleared (0).
PRS0
Control of IICA operation clock (f
MCK
)
Selects
f
CLK
(1 MHz
≤ f
CLK
≤ 20 MHz).
0
1 Selects
f
CLK
/2 (20 MHz < f
CLK
).
Cautions 1. The fastest operation frequency of the IICA operation clock (f
MCK
) is 20 MHz (Max.).
<R>
Set the bit 0 (PRS0) of the IICA control register 01 (IICCTL01) to 1, only when the f
CLK
exceeds 20 MHz.
2. Note the minimum f
CLK
operation frequency when setting the transfer clock.
<R>
The minimum f
CLK
operation frequency for serial interface IICA is determined
according to the mode.
Fast mode:
f
CLK
= 3.5 MHz (MIN.)
Fast mode plus: f
CLK
= 10 MHz (MIN.)
Normal mode: f
CLK
= 1 MHz (MIN.)
Remark IICE0: Bit 7 of IICA control register 00 (IICCTL00)
R01UH0305EJ0200 Rev.2.00
584
Jul 04, 2013