Hynix HMP125U6EFR8C-S6 Merkblatt

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.3 / Nov. 2008                                                                                                                                                                           1
240pin DDR2 SDRAM Unbuffered DIMMs based on 1Gb E version
This Hynix unbuffered Dual In-Line Memory Module (DIMM) series consists of 1Gb version E DDR2
SDRAMs in Fine Ball Grid Array (FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb
version E based DDR2 Unbuffered DIMM series provide a high performance 8 byte interface in 133.35mm
width form factor of industry standard. It is suitable for easy interchange and addition.
FEATURES
ORDERING INFORMATION
Part Name
Density
Org.
# of 
DRAMs
# of 
ranks
Materials
ECC
HMP164U6EFR8C-C4/Y5/S6/S5
512MB
64Mx64
4
1
Halogen free
None
HMP112U6EFR8C-C4/Y5/S6/S5
1GB
128Mx64
8
1
Halogen free
None
HMP112U7EFR8C-C4/Y5/S6/S5
1GB
128Mx72
9
1
Halogen free
ECC
HMP125U6EFR8C-C4/Y5/S6/S5
2GB
256Mx64
16
2
Halogen free
None
HMP125U7EFR8C-C4/Y5/S6/S5
2GB
256Mx72
18
2
Halogen free
ECC
JEDEC standard Double Data Rate2 Syn-
chrnous DRAMs (DDR2 SDRAMs) with 1.8V +/
- 0.1V Power Supply
All inputs and outputs are compatible with 
SSTL_1.8 interface
8 Bank architecture
Posted  CAS
Programmable CAS Latency 3,4,5, 6
OCD (Off-Chip Driver Impedance Adjustment)
ODT (On-Die Termination)
Fully differential clock operations (CK & CK)
Programmable Burst Length 4 / 8 with both 
sequential and interleave mode
Auto refresh and self refresh supported
8192 refresh cycles / 64ms
Serial presence detect with EEPROM
DDR2 SDRAM Package: 60ball 
FBGA(128Mx8),
 84ball FBGA(64Mx16)
133.35 x 30.00 mm form factor
RoHS compliant & Halogen-free