Texas Instruments TMS320C6727 Benutzerhandbuch
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4.13.2 McASP Electrical Data/Timing
TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
4.13.2.1 Multichannel Audio Serial Port (McASP) Timing
and
assume testing over recommended operating conditions (see
and
Table 4-22. McASP Timing Requirements
(1) (2)
NO.
MIN
MAX
UNIT
Cycle time, AHCLKR external, AHCLKR input
20
1
t
c(AHCKRX)
ns
Cycle time, AHCLKX external, AHCLKX input
20
Pulse duration, AHCLKR external, AHCLKR input
7.5
2
t
w(AHCKRX)
ns
Pulse duration, AHCLKX external, AHCLKX input
7.5
Cycle time, ACLKR external, ACLKR input
greater of 2P or 20 ns
3
t
c(ACKRX)
ns
Cycle time, ACLKX external, ACLKX input
greater of 2P or 20 ns
Pulse duration, ACLKR external, ACLKR input
10
4
t
w(ACKRX)
ns
Pulse duration, ACLKX external, ACLKX input
10
Setup time, AFSR input to ACLKR internal
8
Setup time, AFSX input to ACLKX internal
8
Setup time, AFSR input to ACLKR external input
3
5
t
su(AFRXC-ACKRX)
ns
Setup time, AFSX input to ACLKX external input
3
Setup time, AFSR input to ACLKR external output
3
Setup time, AFSX input to ACLKX external output
3
Hold time, AFSR input after ACLKR internal
0
Hold time, AFSX input after ACLKX internal
0
Hold time, AFSR input after ACLKR external input
3
6
t
h(ACKRX-AFRX)
ns
Hold time, AFSX input after ACLKX external input
3
Hold time, AFSR input after ACLKR external output
3
Hold time, AFSX input after ACLKX external output
3
Setup time, AXRn input to ACLKR internal
8
7
t
su(AXR-ACKRX)
Setup time, AXRn input to ACLKR external input
3
ns
Setup time, AXRn input to ACLKR external output
3
Hold time, AXRn input after ACLKR internal
3
8
t
h(ACKRX-AXR)
Hold time, AXRn input after ACLKR external input
3
ns
Hold time, AXRn input after ACLKR external output
3
(1)
ACLKX internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX external input – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX external output – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR internal – ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR external input – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR external output – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
ACLKX external input – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX external output – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR internal – ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR external input – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR external output – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2)
P = SYSCLK2 period
Peripheral and Electrical Specifications
76