Texas Instruments TMS320C642X Benutzerhandbuch

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1.1

Purpose of the Peripheral

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1.2

Features

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1.3

Functional Block Diagram

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1.4

Industry Standard(s) Compliance Statement

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2.1

Bus Structure

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2.2

Clock Generation

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2.3

Clock Synchronization

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2.4

Signal Descriptions

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2.5

START and STOP Conditions

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2.6

Serial Data Formats

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2.7

Endianness Considerations

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2.8

Operating Modes

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2.9

NACK Bit Generation

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2.10

Arbitration

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2.11

Reset Considerations

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2.12

Initialization

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2.13

Interrupt Support

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2.14

DMA Events Generated by the I2C Peripheral

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2.15

Power Management

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2.16

Emulation Considerations

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3.1

I2C Own Address Register (ICOAR)

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3.2

I2C Interrupt Mask Register (ICIMR)

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3.3

I2C Interrupt Status Register (ICSTR)

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3.4

I2C Clock Divider Registers (ICCLKL and ICCLKH)

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3.5

I2C Data Count Register (ICCNT)

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3.6

I2C Data Receive Register (ICDRR)

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3.7

I2C Slave Address Register (ICSAR)

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3.8

I2C Data Transmit Register (ICDXR)

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3.9

I2C Mode Register (ICMDR)

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3.10

I2C Interrupt Vector Register (ICIVR)

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3.11

I2C Extended Mode Register (ICEMDR)

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3.12

I2C Prescaler Register (ICPSC)

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3.13

I2C Peripheral Identification Register (ICPID1)

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3.14

I2C Peripheral Identification Register (ICPID2)

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3

SPRUEN0D – March 2011

© 2011, Texas Instruments Incorporated