Texas Instruments TMS320C6722 Benutzerhandbuch
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Contents
TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
1
TMS320C6727, TMS320C6726, TMS320C6722
4.3
Recommended Operating Conditions
...............
DSPs
........................................................
4.4
Electrical Characteristics
............................
1.1
Features
..............................................
4.5
Parameter Information
..............................
1.2
Description
............................................
4.6
Timing Parameter Symbology
.......................
1.2.1
Device Compatibility
.................................
4.7
Power Supplies
......................................
1.3
Functional Block Diagram
............................
4.8
Reset
................................................
2
Device Overview
.........................................
4.9
Dual Data Movement Accelerator (dMAX)
..........
2.1
Device Characteristics
................................
4.10
External Interrupts
...................................
2.2
Enhanced C67x+ CPU
...............................
4.11
External Memory Interface (EMIF)
..................
2.3
CPU Interrupt Assignments
...........................
4.12
Universal Host-Port Interface (UHPI) [C6727 Only]
.
2.4
Internal Program/Data ROM and RAM
..............
4.13
Multichannel Audio Serial Ports (McASP0, McASP1,
and McASP2)
and McASP2)
........................................
2.5
Program Cache
......................................
4.14
Serial Peripheral Interface Ports (SPI0, SPI1)
......
2.6
High-Performance Crossbar Switch
.................
4.15
Inter-Integrated Circuit Serial Ports (I2C0, I2C1)
...
2.7
Memory Map Summary
.............................
4.16
Real-Time Interrupt (RTI) Timer With Digital
2.8
Boot Modes
..........................................
Watchdog
............................................
2.9
Pin Assignments
....................................
4.17
External Clock Input From Oscillator or CLKIN Pin
2.10
Development
........................................
4.18
Phase-Locked Loop (PLL)
.........................
3
Device Configurations
.................................
5
Application Example
.................................
3.1
Device Configuration Registers
.....................
6
Revision History
......................................
3.2
Peripheral Pin Multiplexing Options
.................
7
Mechanical Data
.......................................
3.3
Peripheral Pin Multiplexing Control
.................
7.1
Package Thermal Resistance Characteristics
.....
4
Peripheral and Electrical Specifications
...........
7.2
Supplementary Information About the 144-Pin RFP
4.1
Electrical Specifications
.............................
PowerPAD™ Package
.............................
4.2
Absolute Maximum Ratings
.........................
7.3
Packaging Information
.............................
6
Contents