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Texas Instruments TMS320C6722 Benutzerhandbuch

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4.15 Inter-Integrated Circuit Serial Ports (I2C0, I2C1)
4.15.1 I2C Device-Specific Information
Peripheral 
Configuration
Bus
Noise
Filter
Noise
Filter
Clock Prescaler
I2CPSCx
Prescaler
Register
Bit Clock Generator
I2CCLKHx
Clock Divide
High Register
I2CCLKLx
Clock Divide
Low Register
Control
I2CCOARx
Own Address
Register
I2CSARx
Slave Address
Register
I2CCMDRx
Mode Register
I2CEMDRx
Extended Mode
Register
I2CCNTx
Data Count
Register
I2CPID1
Peripheral ID
Register 1
I2CPID2
Peripheral ID
Register 2
Transmit
I2CXSRx
Transmit Shift
Register
I2CDXRx
Transmit Buffer
Receive
I2CDRRx
Receive Buffer
I2CRSRx
Receive Shift
Register
I2Cx_SCL
I2Cx_SDA
C672x I2C Module
Control
Interrupt/DMA
I2CIERx
Interrupt Enable
Register
I2CSTRx
Interrupt Status
Register
I2CSRCx
Interrupt Source
Register
Control
I2CPFUNC
Pin Function
Register
I2CPDIR
Pin Direction
Register
I2CPDIN
Pin Data In
Register
I2CPDOUT
Pin Data Out
Register
I2CPDSET
Pin Data Set
Register
I2CPDCLR
Pin Data Clear
Register
Interrupt DMA
Requests
TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
Having two I2C modules on the C672x simplifies system architecture, since one module may be used by
the DSP to control local peripherals ICs (DACs, ADCs, etc.) while the other may be used to communicate
with other controllers in a system or to implement a user interface.
is block diagram of the
C672x I2C Module.
Each I2C port supports:
•
Compatible with Philips
®
I2C Specification Revision 2.1 (January 2000)
•
Fast Mode up to 400 Kbps (no fail-safe I/O buffers)
•
Noise Filter to Remove Noise 50 ns or less
•
Seven- and Ten-Bit Device Addressing Modes
•
Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality
•
Events: DMA, Interrupt, or Polling
•
General-Purpose I/O Capability if not used as I2C
CAUTION
The C672x I2C pins use a standard
±
8 mA LVCMOS buffer, not the slow I/O buffer
defined in the I2C specification. Series resistors may be necessary to reduce noise at
the system level.
Figure 4-37. I2C Module Block Diagram
Peripheral and Electrical Specifications
93