Xilinx UG015 Benutzerhandbuch
Virtex-II Prototype Platform
29
UG015 / PN0401974 (v1.1) January 14, 2003
1-800-255-7778
User Programmable Pins
R
Breakout Area 3
GCLK7S
T8
GCLK7S
AA11
GCLK7S
AC13
GCLK7S
AK18
Breakout Area 4
GCLK0P
T9
GCLK0P
AB12
GCLK0P
AD14
GCLK0P
AK17
Table 15:
Clock Pins and Corresponding I/Os (Continued)
FG256
FG456
FG676
FF1152
Clock Pins
Clock
Name
Name
Pin
Number
Clock
Name
Name
Pin
Number
Clock
Name
Name
Pin
Number
Clock
Name
Name
Pin
Number