Cypress CY8CTMG120 Benutzerhandbuch

 
 
 

 

September 25, 2008 

 Document No. 001-49038 Rev. ** 

2 

1.  Internal Main Oscillator (IMO) tolerance deviation at temperature extremes. 
 

 

 

Asynchronous digital communication interfaces may fail framing beyond 0 to 70°C. This problem does not 
affect end product usage between 0 and 70°C. 

 

PARAMETERS AFFECTED 
The IMO frequency tolerance. The worst case deviation when operated below 0°C and above +70°C and 
within the upper and lower data sheet temperature range is ±5%.  

 

TRIGGER CONDITION 
The asynchronous Rx/Tx clock source IMO frequency tolerance may deviate beyond the data sheet limit 
of ±4% when operated beyond the temperature range of 0 to +70°C. 

 

SCOPE OF IMPACT 
This problem may affect UART, IrDA, and FSK implementations. 

 

 

Implement a quartz crystal stabilized clock source on at least one end of the asynchronous digital 
communications interface. 

 

FIX STATUS 
The cause of this problem and its solution has been identified. Silicon fix is planned to correct the 
deficiency in silicon. 

 

PROBLEM DEFINITION 
When the device is operating at 4.75V to 5.25V and the 3.3V regulator is enabled, a short low pulse may 
be created on the DP signal line during device wakeup. The 15 µs to 20 µs low pulse of the DP line may 
be interpreted by the host computer as a de-attach or the beginning of a wakeup. 

 

 

The bandgap reference voltage used by the 3.3V regulator decreases during sleep due to leakage. Upon 
device wakeup, the bandgap is re-enabled and after a delay for settling, the 3.3V regulator is enabled. On 
some devices the 3.3V regulator that is used to generate the USB DP signal may be enabled before the 
bandgap is fully stabilized. This can cause a low pulse on the regulator output and DP signal line until the 
bandgap stabilizes. In applications where Vdd is 3.3V, the regulator is not used; therefore, the DP low 
pulse is not generated. 

 

 

To prevent the DP signal from pulsing low, keep the bandgap enabled during sleep. The most efficient 
method is to set the No Buzz bit in the OSC_CR0 register. The No Buzz bit keeps the bandgap powered 
and output stable during sleep. Setting the No Buzz bit results in a nominal 100 µA increase to sleep 
current. Leaving the analog reference block enabled during sleep also resolves this issue because it 
forces the bandgap to remain enabled. An example to disable the No Buzz bit is as follows. 

 

 

 

M8C_SetBank1 

 

or    reg[OSC_CR0], 0x20 

 

M8C_SetBank0 

OSC_CR0 |= 0x20;