Cypress CY14B104M Benutzerhandbuch
PRELIMINARY
CY14B104K, CY14B104M
Document #: 001-07103 Rev. *K
Page 18 of 31
Switching Waveforms
Figure 8. SRAM Read Cycle 2: CE Controlled
Figure 9. SRAM Write Cycle 1: WE Controlled
Address Valid
Address
Data Output
Output Data Valid
Standby
Active
High Impedance
CE
OE
BHE, BLE
I
CC
t
HZCE
t
RC
t
ACE
t
AA
t
LZCE
t
DOE
t
LZOE
t
DBE
t
LZBE
t
PU
t
PD
t
HZBE
t
HZOE
Data Output
Data Input
Input Data Valid
High Impedance
Address Valid
Address
Previous Data
t
WC
t
SCE
t
HA
t
BW
t
AW
t
PWE
t
SA
t
SD
t
HD
t
HZWE
t
LZWE
WE
BHE, BLE
CE
Notes
21. CE or WE must be >V
IH
during address transitions.