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Texas Instruments ADS61B23EVM Benutzerhandbuch

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Circuit Description
Table 2. Jumpers
Description
Reference Designator
Default Selection
Optional Selection
Parallel mode: SEN pin
J1
5–6, Offset binary, CMOS output
Multiple choices
voltage bias
SEN control
J2
2–3, EVM controlled
1–2, USB or FPGA
controlled
ADC control mode
J3
2–3, Parallel mode
1–2, serial mode
Parallel mode: SCLK pin
J4
1–2, 0-dB Gain, Int Ref
Multiple choices
voltage bias
ADS61xx/ADS61B23
J5
1–2, ADS61xx/ADS61B23 powered on
2–3, ADS61xx/ADS61B23
power down
powered off
SDATA control
J6
1–2, USB or FPGA controlled
2–3, EVM controlled
SCLK control
J7
2–3, EVM controlled
2–3, USB or FPGA
controlled
Table 3. Surface-Mount Jumpers
Description
Reference Designator
Default Selection
Optional Selection
JP1
Probe point for CDCP1803 output
Clock input path selection
JP2
1–2, transformer coupled path
2–3, CDCP1803 path
Clock input path selection
JP3
1–2, transformer coupled path
2–3, CDCP1803 path
Clock input path selection
JP4
1–2, transformer coupled path
2–3, CDCP1803 path
Analog input path
JP5
1–2, transformer coupled input path
2–3, THS4509 path
Analog input path
JP6
1–2, transformer coupled input path
2–3, THS4509 path
THS4509 power down
JP7
2–3, THS4509 powered down
1–2, THS4509 powered
on
CDCP1803 power down
JP8
2–3, CDCP1803 powered down
1–2, CDCP1803 powered
on
SLAU206B – September 2007 – Revised April 2008
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