Texas Instruments SCAU020 Benutzerhandbuch
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ChronosGUI
frequency should be entered here in this format: xx.xxx (specified in MHz).
Step 3.
Output Calculator and Apply PLL Settings.
The second row of calculations is used to obtain the PLL settings necessary to achieve a particular
output frequency provided a given input frequency to CDCE421. The input must be entered in the
second row as well as the location provided at the input of the PLL block diagram. After the Calculate
button is pressed, the adjacent drop-down menu populates with several choices for the given input.
The desired output can then be chosen from this list. Choosing one output sets the divider settings
within the PLL. Clicking Apply next to the drop-down menu results in writing the PLL settings to the
SRAM. If LVPECL output is desired, click Output Type until the LVPECL option displays. This option
automatically enables onboard LVPECL termination. If LVDS output is desired, use Output Type to
select the LVDS option.
output frequency provided a given input frequency to CDCE421. The input must be entered in the
second row as well as the location provided at the input of the PLL block diagram. After the Calculate
button is pressed, the adjacent drop-down menu populates with several choices for the given input.
The desired output can then be chosen from this list. Choosing one output sets the divider settings
within the PLL. Clicking Apply next to the drop-down menu results in writing the PLL settings to the
SRAM. If LVPECL output is desired, click Output Type until the LVPECL option displays. This option
automatically enables onboard LVPECL termination. If LVDS output is desired, use Output Type to
select the LVDS option.
Step 4.
PLL Bandwidth Select.
If the user wants to adjust the PLL bandwidth, click the Loop Filter block, bringing a pop-up screen as
shown in
shown in
.
Figure 6. Chronos GUI—Loop Filter Configuration Pop-Up
For a clean reference input to the CDCE421 (for example, from an oscillator or crystal), the maximum
bandwidth and phase margin setting must be used: 400kHz bandwidth and 80 degrees. The Phase
Frequency Detector (PFD) charge pump current must be set to its maximum, 224
bandwidth and phase margin setting must be used: 400kHz bandwidth and 80 degrees. The Phase
Frequency Detector (PFD) charge pump current must be set to its maximum, 224
µ
A. The PFD charge
pump current can be set by clicking on the PDF Charge Pump block, presenting a drop-down menu
with the various charge pump current settings.
For a dirty reference input to the CDCE421, the minimum bandwidth of 50kHz must be used.
Additionally, to reduce the output jitter for a dirty input, the phase margin can also be reduced to near
its minimum (30 degrees), depending on the integration limits of the jitter that are important for a given
application. To reduce the output jitter further, the charge pump current can be reduced to its minimum
(56
with the various charge pump current settings.
For a dirty reference input to the CDCE421, the minimum bandwidth of 50kHz must be used.
Additionally, to reduce the output jitter for a dirty input, the phase margin can also be reduced to near
its minimum (30 degrees), depending on the integration limits of the jitter that are important for a given
application. To reduce the output jitter further, the charge pump current can be reduced to its minimum
(56
µ
A), depending on the integration limits of the jitter.
Step 5.
Write to CDCE421 EEPROM.
To write any particular setting to the EEPROM (locking or nonlocking), the Device_EEPROM
drop-down menu (at the top of the screen) must be selected. This menu contains the items Write
settings to EEPROM (No locking) and Write settings to EEPROM (Locking). Choose the appropriate
option after setting the desired PLL configurations to write to the EEPROM in its appropriate mode.
drop-down menu (at the top of the screen) must be selected. This menu contains the items Write
settings to EEPROM (No locking) and Write settings to EEPROM (Locking). Choose the appropriate
option after setting the desired PLL configurations to write to the EEPROM in its appropriate mode.
10.9MHz–1175MHz Low Phase Noise Clock Evaluation Board
10
SCAU020 – March 2007