Intel CM8063501292204 Benutzerhandbuch

 

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Intel® Xeon® Processor E5-1600 v2/E5-2600 v2 Product Families 

Datasheet Volume One of Two

The VR may change its configuration to meet the processor’s power needs with greater 

efficiency. For example, it may reduce the number of active phases, transition from 
CCM (Continuous Conduction Mode) to DCM (Discontinuous Conduction Mode) mode, 

reduce the switching frequency or pulse skip, or change to asynchronous regulation. 

For example, typical power states are 00h = run in normal mode; a command of 01h= 
shed phases mode, and an 02h=pulse skip.

The VR may reduce the number of active phases from PS(00h) to PS(01h) or PS(00h) 
to PS(02h) for example. There are multiple VR design schemes that can be used to 

maintain a greater efficiency in these different power states, please work with your VR 

controller suppliers for optimizations.

The SetPS command sends a byte that is encoded as to what power state the VR 

should transition to.

If a power state is not supported by the controller, the slave should acknowledge with 
command rejected (11b)

Note the mapping of power states 0-n will be detailed in the compatible VR12.0 PWM 

controller. 

If the VR is in a low power state and receives a SetVID command moving the VID up 

then the VR exits the low power state to normal mode (PS0) to move the voltage up as 

fast as possible. The processor must re-issue low power state (PS1 or PS2) command if 
it is in a low current condition at the new higher voltage. See 

 for VR power 

state transitions.

The processor addresses 4 different voltage rail control segments within VR12  

(VCC, VCCD_01, VCCD_23, and VSA). The SVID data packet contains a 4-bit 

addressing code:

00

V

cc

01

V

sa