Intel CM8063501292204 Benutzerhandbuch

Intel® Xeon® Processor E5-1600 v2/E5-2600 v2 Product Families

135

Datasheet Volume One of Two

 

PCI Express*

PCI Express* interface signals. These signals are compatible with PCI Express 3.0 

Signalling Environment AC Specifications and are AC coupled. The buffers are not 

3.3-V tolerant. Refer to the PCIe specification.

Reference

Voltage reference signal.

SSTL

Source Series Terminated Logic (JEDEC SSTL_15)

1.

Qualifier for a buffer type.

Differential

SSTL Output

DDR{0/1/2/3}_CLK_D[N/P][3:0]

Single ended

SSTL Output

DDR{0/1/2/3}_BA[2:0]
DDR{0/1/2/3}_CAS_N
DDR{0/1/2/3}_MA[15:00]
DDR{0/1/2/3}_MA_PAR
DDR{0/1/2/3}_RAS_N
DDR{0/1/2/3}_WE_N

CMOS1.5v Output

DDR_RESET_C{01/23}_N

Single ended

CMOS1.5v Output

DDR{0/1/2/3}_CS_N[9:0]
DDR{0/1/2/3}_ODT[5:0]
DDR{0/1/2/3}_CKE[5:0]

Reference Output

DDR_VREFDQTX_C{01/23}

Reference Input

DDR_VREFDQRX_C{01/23}
DDR{01/23}_RCOMP[2:0] 

Differential

SSTL Input/Output

DDR{0/1/2/3}_DQS_D[N/P][17:00]

Single ended

SSTL Input/Output

DDR{0/1/2/3}_DQ[63:00]
DDR{0/1/2/3}_ECC[7:0]

SSTL Input

DDR{0/1/2/3}_PAR_ERR_N

Single ended

CMOS1.5v Input

DRAM_PWR_OK_C{01/23}

Differential

PCI Express* Input

PE1A_RX_D[N/P][3:0]
PE1B_RX_D[N/P][7:4]
PE2A_RX_D[N/P][3:0]
PE2B_RX_D[N/P][7:4]
PE2C_RX_D[N/P][11:8]
PE2D_RX_D[N/P][15:12]
PE3A_RX_D[N/P][3:0]
PE3B_RX_D[N/P][7:4]
PE3C_RX_D[N/P][11:8]
PE3D_RX_D[N/P][15:12]