Intel 80C188XL Benutzerhandbuch

8-6

This example illustrates priority resolution. Assume these initial conditions:

•

the Interrupt Control Unit has been initialized

•

no interrupts are pending

•

no In-Service bits are set

•

the Interrupt Enable bit is set

•

all interrupts are unmasked

•

the default priority scheme is being used

•

the Priority Mask register is set to the lowest priority (seven)

The example uses two external interrupt sources, INT0 and INT3, to describe the process.

1.

A low-to-high transition on INT0 sets its Interrupt Request bit. The interrupt is now
pending.

2.

Because INT0 is the only pending interrupt, it meets all the priority criteria. The Interrupt
Control Unit asserts the interrupt request to the CPU and waits for an acknowledge.

3.

The CPU acknowledges the interrupt.

4.

The Interrupt Control Unit passes the interrupt type (in this case, type 12) to the CPU.

5.

The Interrupt Control Unit clears the INT0 bit in the Interrupt Request register and sets the
INT0 bit in the In-Service register.

6.

The CPU executes the interrupt processing sequence and begins executing the interrupt
handler for INT0.

7.

During execution of the INT0 interrupt handler, a low-to-high transition on INT3 sets its
Interrupt Request bit.

8.

The Interrupt Control Unit determines that INT3 has a lower priority than INT0, which is
currently executing (INT0’s In-Service bit is set). INT3 does not meet the priority criteria,
so no interrupt request is sent to the CPU.  (If INT3were programmed with a higher
priority than INT0, the request would be sent.) INT3 remains pending in the Interrupt
Request register.

9.

The INT0 interrupt handler completes and sends an EOI command to clear the INT0 bit in
the In-Service register.

10. INT3 is still pending and now meets all the priority criteria. The Interrupt Control Unit

asserts the interrupt request to the CPU and the process begins again.