Intel 80C188XL Benutzerhandbuch
DIRECT MEMORY ACCESS UNIT
10-12
Figure 10-8. DMA Source Pointer (Low-Order Bits)
The address space referenced by the source and destination pointers is programmed in the DMA
Control Register for the channel (see Figure 10-11 on page 10-15). The SMEM and DMEM bits
control the address space (memory or I/O) for source pointer and destination pointer, respective-
ly.
Control Register for the channel (see Figure 10-11 on page 10-15). The SMEM and DMEM bits
control the address space (memory or I/O) for source pointer and destination pointer, respective-
ly.
Automatic pointer indexing is also controlled by the DMA Control Register. Each pointer has two
bits, increment and decrement, that control the indexing. If the increment and decrement bits for
a pointer are programmed to the same value, then the pointer remains constant. The programmed
data width (byte or word) for the channel automatically controls the amount that a pointer is in-
cremented or decremented.
bits, increment and decrement, that control the indexing. If the increment and decrement bits for
a pointer are programmed to the same value, then the pointer remains constant. The programmed
data width (byte or word) for the channel automatically controls the amount that a pointer is in-
cremented or decremented.
Register Name:
DMA Source Address Pointer (Low)
Register Mnemonic:
DxSRCL
Register Function:
Contains the lower 16 bits of the DMA Source pointer.
Bit
Mnemonic
Bit Name
Reset
State
Function
DSA15:0
DMA
Source
Address
Source
Address
XXXXH
DSA15:0 are driven on the lower 16 bits of the
address bus during the fetch phase of a DMA
transfer.
address bus during the fetch phase of a DMA
transfer.
15
0
D
S
A
S
A
1
D
S
A
S
A
2
D
S
A
S
A
3
D
S
A
S
A
0
D
S
A
S
A
5
D
S
A
S
A
6
D
S
A
S
A
7
D
S
A
S
A
4
D
S
A
S
A
9
D
S
A
S
A
1
0
0
D
S
A
S
A
1
1
1
D
S
A
S
A
8
D
S
A
S
A
1
3
3
D
S
A
S
A
1
4
4
D
S
A
S
A
1
5
5
D
S
A
S
A
1
2
2
A1177-0A