Samsung 3.5" hard disk drives Benutzerhandbuch

DISK DRIVE OPERATION 

 

SpinPoint V40 Product Manual

31

 
The SID2001 supports a programmable 10-way interleaved Reed-Solomon ECC.  The code is capable of 
correcting up to ten 3 bytes, one 30 bytes bursts in hardware up to or 60 bytes correction with erasure pointer.  
The Disk ECC block also supports 32 bits of ESN (Embedded Sector Number) to the ECC generator to allow 
for greater data integrity in a headerless environment. Error detection and correction is handled in the Disk 
Control block.  Automatic on-the-fly hardware correction will take place for up to three symbols in error per 
interleave.  Correction is guaranteed to complete before the ECC Field of the sector following the sector 
where the error occurred utilizing standard ATA size sectors.  Optional burst limiting can be used to decrease 
the probability on misdetection and mis-correction. An added feature of the SID2001 ECC block is the ability 
to log corrected ECC errors. 
 

 
The frequency synthesizer is a clock frequency generation circuit used to generate a DSP clock, AT disk 
controller and servo clock from the External Reference clock input.  
 

 
Power management features are incorporated into each block of the SID2001.  This allows the designer to 
tailor the amount of power management to the specified design.  Other power management features include: 

•

  Independent power management control for each block. 

•

  DSP block powered down and up when needed. 

•

  Disk Sequencer and associated disk logic powered up when the Disk Sequencer is started. 

•

  Weak pull-up structure on input pins to prevent undesirable power consumption due to floating CMOS 

inputs. 

 
 

 
The Read/Write IC, shown in Figure 5-3 provides read/write-processing functions for the drive.  The 
Read/Write IC receives the RD GATE and WR GATE signals, write data, and servo AGC and gates from the 
Interface Controller. The Read/Write IC sends decoded read data and the read reference clock.  It receives 
write data from the Interface Controller. 
 
The 88C5200 is a sampled-data digital PRML channel designed to work with a disk controller and a 
read/write preamplifier to provide the signal processing elements required to build a state 
of the art high density, high speed disk drive.  The 88C5200 implements a noise predictive, PRML Viterbi 
read channel (supporting) zone-bit recording ,