Freescale Semiconductor MC68HC908MR16 Benutzerhandbuch
Central Processor Unit (CPU)
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
86
Freescale Semiconductor
CLR opr
CLRA
CLRX
CLRH
CLR opr,X
CLR ,X
CLR opr,SP
CLRA
CLRX
CLRH
CLR opr,X
CLR ,X
CLR opr,SP
Clear
M
← $00
A
← $00
X
← $00
H
← $00
M
← $00
M
← $00
M
← $00
0 – – 0 1 –
DIR
INH
INH
INH
IX1
IX
SP1
INH
INH
INH
IX1
IX
SP1
3F
4F
5F
4F
5F
8C
6F
7F
7F
9E6F
dd
ff
ff
3
1
1
1
3
2
4
1
1
1
3
2
4
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
CMP opr,SP
CMP opr,SP
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
CMP opr,SP
CMP opr,SP
Compare A with M
(A) – (M)
– –
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
EXT
IX2
IX1
IX
SP1
SP2
A1
B1
C1
D1
E1
F1
B1
C1
D1
E1
F1
9EE1
9ED1
9ED1
ii
dd
hh ll
ee ff
ff
dd
hh ll
ee ff
ff
ff
ee ff
ee ff
2
3
4
4
3
2
4
5
3
4
4
3
2
4
5
COM opr
COMA
COMX
COM opr,X
COM ,X
COM opr,SP
COMA
COMX
COM opr,X
COM ,X
COM opr,SP
Complement (One’s Complement)
M
← (M) = $FF – (M)
A
← (A) = $FF – (M)
X
← (X) = $FF – (M)
M
← (M) = $FF – (M)
M
← (M) = $FF – (M)
M
← (M) = $FF – (M)
0 – –
1
DIR
INH
INH
IX1
IX
SP1
INH
INH
IX1
IX
SP1
33
43
53
63
73
43
53
63
73
9E63
dd
ff
ff
4
1
1
4
3
5
1
1
4
3
5
CPHX #opr
CPHX opr
CPHX opr
Compare H:X with M
(H:X) – (M:M + 1)
– – IMM
DIR
65
75
75
ii ii+1
dd
dd
3
4
4
CPX #opr
CPX opr
CPX opr
CPX ,X
CPX opr,X
CPX opr,X
CPX opr,SP
CPX opr,SP
CPX opr
CPX opr
CPX ,X
CPX opr,X
CPX opr,X
CPX opr,SP
CPX opr,SP
Compare X with M
(X) – (M)
– –
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
EXT
IX2
IX1
IX
SP1
SP2
A3
B3
C3
D3
E3
F3
B3
C3
D3
E3
F3
9EE3
9ED3
9ED3
ii
dd
hh ll
ee ff
ff
dd
hh ll
ee ff
ff
ff
ee ff
ee ff
2
3
4
4
3
2
4
5
3
4
4
3
2
4
5
DAA
Decimal Adjust A
(A)
10
U – –
INH
72
2
DBNZ opr,rel
DBNZA rel
DBNZX rel
DBNZ opr,X,rel
DBNZ X,rel
DBNZ opr,SP,rel
DBNZA rel
DBNZX rel
DBNZ opr,X,rel
DBNZ X,rel
DBNZ opr,SP,rel
Decrement and Branch if Not Zero
A
← (A) – 1 or M ← (M) – 1 or X ← (X) – 1
PC
← (PC) + 3 + rel ? (result) ≠ 0
PC
← (PC) + 2 + rel ? (result) ≠ 0
PC
← (PC) + 2 + rel ? (result) ≠ 0
PC
← (PC) + 3 + rel ? (result) ≠ 0
PC
← (PC) + 2 + rel ? (result) ≠ 0
PC
← (PC) + 4 + rel ? (result) ≠ 0
– – – – – –
DIR
INH
INH
IX1
IX
SP1
INH
INH
IX1
IX
SP1
3B
4B
5B
6B
7B
4B
5B
6B
7B
9E6B
dd rr
rr
rr
ff rr
rr
ff rr
rr
rr
ff rr
rr
ff rr
5
3
3
5
4
6
3
3
5
4
6
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
DEC opr,SP
DECA
DECX
DEC opr,X
DEC ,X
DEC opr,SP
Decrement
M
← (M) – 1
A
← (A) – 1
X
← (X) – 1
M
← (M) – 1
M
← (M) – 1
M
← (M) – 1
– – –
DIR
INH
INH
IX1
IX
SP1
INH
INH
IX1
IX
SP1
3A
4A
5A
6A
7A
4A
5A
6A
7A
9E6A
dd
ff
ff
4
1
1
4
3
5
1
1
4
3
5
DIV
Divide
A
← (H:A)/(X)
H
← Remainder
– – – –
INH
52
7
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
EOR opr,SP
EOR opr,SP
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
EOR opr,SP
EOR opr,SP
Exclusive OR M with A
A
← (A
⊕
M)
0 – –
–
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
EXT
IX2
IX1
IX
SP1
SP2
A8
B8
C8
D8
E8
F8
B8
C8
D8
E8
F8
9EE8
9ED8
9ED8
ii
dd
hh ll
ee ff
ff
dd
hh ll
ee ff
ff
ff
ee ff
ee ff
2
3
4
4
3
2
4
5
3
4
4
3
2
4
5
INC opr
INCA
INCX
INC opr,X
INC ,X
INC opr,SP
INCA
INCX
INC opr,X
INC ,X
INC opr,SP
Increment
M
← (M) + 1
A
← (A) + 1
X
← (X) + 1
M
← (M) + 1
M
← (M) + 1
M
← (M) + 1
– – –
DIR
INH
INH
IX1
IX
SP1
INH
INH
IX1
IX
SP1
3C
4C
5C
6C
7C
4C
5C
6C
7C
9E6C
dd
ff
ff
4
1
1
4
3
5
1
1
4
3
5
Table 7-1. Instruction Set Summary (Sheet 3 of 6)
Source
Form
Operation
Description
Effect
on CCR
Addre
s
s
Mode
Op
co
de
Op
era
n
d
C
y
cl
es
V H I N Z C