Fujitsu FR81S Benutzerhandbuch
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
6. Operation of CSIO
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
220
[1] Master operation (Set SCR:MS=0, SMR:SCKE=1, SCSCR:CSOE=1, SCSCR:CSENn*=1)
*: n is the serial chip select pin number to be used.
Transmission operation
(1) With serial data output enabled (SMR:SOE=1), transmission operation enabled (SCR:TXE=1), and
reception operation disabled (SCR:RXE=0), writing transmission data to TDR sets SSR:TDRE=0. After
that, the serial chip select pin (SCS) become active at the same time the first bit is output, and the
transmission operation starts after the setup time of the serial chip select pin has passed. Then, the
transmission data is output in synchronization with a falling edge of the serial clock (SCK) output.
(2) Half a cycle before a falling edge of the first serial clock (SCK), SSR:TDRE is set to 1 and, if the
transmission interrupt is enabled (SCR:TIE=1), a transmission interrupt request is output. At this time, the
transmission data in the second byte can be written.
(3) The transmission operation is terminated after the data transmission is completed as many as the number
of times set with TBYTE.
(4) Then, after the hold time of serial chip select pin has passed, the serial chip select pin (SCS) become
inactive. However, if the serial chip select active level (SCSCR:SCAM=1) is maintained at this time, the
serial chip select pin (SCS) maintains its active state.
Reception operation
(1) With serial data output disabled (SMR:SOE=0), transmission operation enabled (SCR:TXE=1), and
reception operation enabled (SCR:RXE=1), writing dummy data to TDR makes the serial chip select pin
(SCS) active and starts the reception operation after the setup time of that pin has passed. Starting the
reception operation samples the reception data at a rising edge of the serial clock (SCK) output.
(2) Receiving the last bit sets SSR:RDRF=1 and, if the reception interrupt is enabled (SCR:RIE=1), outputs a
reception interrupt request.
At this time, the reception data (RDR) can be read.
(3) Reading the reception data (RDR) clears SSR:RDRF to "0".
(4) The reception operation is terminated after the data reception is completed as many as the number of
times set with TBYTE.
(5) Then, after the hold time of serial chip select pin has passed, the serial chip select pin (SCS) become
inactive. However, if the serial chip select active level (SCSCR:SCAM=1) is maintained at this time, the
serial chip select pin (SCS) maintains its active state.
Notes:
⋅
If only reception operation is to be performed, write dummy data to TDR to output the serial clock
(SCK).
⋅
When transmission/reception FIFO is enabled, setting the FBYTE register to the number of frames to be
transferred outputs as many frames of serial clock (SCK) as the setting.
Transmission/Reception operation
(1) To perform transmission and reception at the same time, enable serial data output (SMR:SOE=1) and
enable transmission/reception operation (SCR:TXE, RXE=1).
(2) When transmission data is written in TDR, SSR:TDRE=0 is set. After that, the serial chip select pin
(SCS) become active at the same time the first bit is output, and the transmission/reception operation
starts after the setup time of the serial chip select pin has passed. Then, the transmission data is output in
synchronization with a falling edge of the serial clock (SCK) output. Half a cycle before a rising edge of
the first serial clock, SSR:TDRE is set to 1 and, if the transmission interrupt is enabled (SCR:TIE=1), a
transmission interrupt request is output. At this time, the transmission data in the second byte can be
written.
MB91520 Series
MN705-00010-1v0-E
1533