Fujitsu FR81S Benutzerhandbuch
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
8. Operation of I2C
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
334
8.3.2. Slave Address Output
When a start condition is output, the data contained in the TDR register is output as the address, beginning
with bit7. If FIFO is enabled, the data first written in the TDR register is output. Bit0 is used to indicate the
data direction bit (R/W). If the data direction bit (R/W) is "0", the data is in the writing direction (from
master to slave). Set the address for the TDR register before "1" is written to IBCR:MSS or IBCR:SCC.
Figure 8-9 Address and Data Direction
Address and Data Direction (when FIFO is Disabled)
1 2 3 4 5 6 7 8
SCL
SDA A6(D7) A5(D6) A4(D5) A3(D4) A2(D3) A1(D2) A0(D1) R/W(D0) ACK
BB bit
MSS bit (*1)
TDRE bit
INT bit
<reserve address detect>
RSA bit
RDRF bit
INT bit
A6-A0:address
D7-D0:TDR rehister bit
R/W:data direction (“L":write direction)
ACK:Acknowledgment(acknowledgment and output from slave for “L")
*1:Set the address to the TDR register before writing “1” to the MSS bit.
SCL is “L” while INT is "1"
MB91520 Series
MN705-00010-1v0-E
1647