Fujitsu FR81S Benutzerhandbuch
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
8. Operation of I2C
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
362
8.3.6. Arbitration Lost
If data of the master device is hit by data from another master device and if the data that is different from
the send data is received, it will be determined to be an arbitration lost. The IBCR:MSS bit is set to "0" and
the IBCR:AL bit is set to "1" so that the device can operate in the slave mode.
The IBCR:AL bit is cleared to "0" if:
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The IBCR:MSS bit is set to "1"
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The IBCR:INT bit is set to "0".
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The IBCR:SPC bit is set to "0" when IBCR:AL="1" and IBCR:SPC="1".
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The I2C interface operation is disabled (ISMK:EN bit="0").
If an arbitration lost occurs, the interrupt flag (IBCR:INT) will be set to "1" and the SCL of I
2
C bus will be
set to "L" based on the IBCR:WSEL setting.
8.3.7. Wait of the Master Mode
In the case where both of conditions below are met, wait the master mode while IBSR:BB bit is "1" and
transmit a start condition after the IBSR:BB became "0".
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When "1" is set to IBCR:MSS bit while IBSR:BB bit is "1"
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The operation is not in slave mode
Whether or not the master mode is in a wait can be determined with IBCR:MSS bit and IBCR:ACT bit
(IBCR:MSS="1" and IBCR:ACT="0" mean a wait). Operating in slave mode after IBCR:MSS bit is set to
"1", set IBSR:AL bit to "1", IBCR:MSS bit to "0", and IBCR:ACT bit to "1".
MB91520 Series
MN705-00010-1v0-E
1675