Fujitsu FR81S Benutzerhandbuch
CHAPTER 41: CAN
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: CAN
FUJITSU SEMICONDUCTOR CONFIDENTIAL
12
Address
Registers
Note
+0
+1
+2
+3
Base-addr + 4C
H
IF2 message control register
(IF2MCTR)
Reserved bits
bit[15:8]
bit[7:0]
bit[7:0]
bit[15:8]
See the
IF2MCTR.
See the
IF2MCTR.
-
-
Reset: 00
H
Reset: 00
H
Reset: 00
H
Reset: 00
H
Base-addr + 50
H
IF2 data A register 1
(IF2DTA1)
IF2 data A register 2
(IF2DTA2)
Byte order:
Big Endian
bit[7:0]
bit[15:8]
bit[7:0]
bit[15:8]
Data[0]
Data[1]
Data[2]
Data[3]
Reset: 00
H
Reset: 00
H
Reset: 00
H
Reset: 00
H
Base-addr + 54
H
IF2 data B register 1
(IF2DTB1)
IF2 data B register 2
(IF2DTB2)
Byte order:
Big Endian
bit[7:0]
bit[15:8]
bit[7:0]
bit[15:8]
Data[4]
Data[5]
Data[6]
Data[7]
Reset: 00
H
Reset: 00
H
Reset: 00
H
Reset: 00
H
Base-addr + 60
H
IF2 data A register 2
(IF2DTA2)
IF2 data A register 1
(IF2DTA1)
Byte order:
Little Endian
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
Data[3]
Data[2]
Data[1]
Data[0]
Reset: 00
H
Reset: 00
H
Reset: 00
H
Reset: 00
H
Base-addr + 64
H
IF2 data B register 2
(IF2DTB2)
IF2 data B register 1
(IF2DTB1)
Byte order:
Little Endian
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
Data[7]
Data[6]
Data[5]
Data[4]
Reset: 00
H
Reset: 00
H
Reset: 00
H
Reset: 00
H
MB91520 Series
MN705-00010-1v0-E
1705