Fujitsu FR81S Benutzerhandbuch
CHAPTER 47: ON CHIP DEBUGER (OCD)
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: ON CHIP DEBUGGER : OCD
FUJITSU SEMICONDUCTOR CONFIDENTIAL
21
5.2. Overview of DEBUG I/F
The overview of DEBUG I/F is shown.
DEBUG I/F is a single-wire debug interface that connects MCU to a tool via one wire (+GND). MCU uses
one pin as the one for the debug interface.
DEBUG I/F is a two-way pin and provides the communication function and special sequence function.
Communication uses the serial transmission method (UART). In the normal UART mode, the communication
baud rate is obtained by division clocks that are based on the main source oscillation clock of MCU. In the
high-speed UART mode and in phase modulation UART (Manchester encode UART), the division clock is
based on the PLL clock.
The special sequence includes chip reset sequence and stall. There are the function that MCU notifies the
INIT generation and the function to detect the debug mode that activated after releasing INIT in the chip reset
sequence. The stall function provides communication stall and forced break requests from the tool, and
communication error notification from MCU.
The main DEBUG I/F functions are shown below.
⋅
Chip reset sequence function (INIT notification, mode command)
⋅
UART function (normal UART, high-speed UART, phase modulation UART)
⋅
Stall request (communication stall request, forced break request, communication error notification)
⋅
Auto negotiation mode function (communication form notification)
The two-way pin of DEBUG I/F is accomplished by N-ch open-drain output. The DEBUG I/F pin is pulled up
on a user system. It is pulled up with a tool during tool connection.
For the tool connection, see Figure 3-2 OCD Connection Diagram.
MB91520 Series
MN705-00010-1v0-E
2032