Fujitsu FR81S Benutzerhandbuch
CHAPTER 51: TIMING PROTECTION UNIT
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : TIMING PROTECTION UNIT
FUJITSU SEMICONDUCTOR CONFIDENTIAL
8
4.2. TPU Lock Status Register : TPULST
The bit configuration of TPU lock status register is shown below.
TPULST : Address 0904
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
LST
Initial value
0
0
0
0
0
0
0
0
Attribute
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R,W0
It is a register that shows the lock status of TPU.
This register is read only, and writing to the register has no influence in operation.
[bit7 to bit1] (Reserved) : (Reserved bit)
These bits are reserved bits. When writing to those bits, 0 must be set. The readout value is always 0.
[bit0] LST (Lock Status) : Lock status display
It is shown whether access of the TPU control register is locked.
LST
Lock Status
0
Access permission
1
Access prohibition
MB91520 Series
MN705-00010-1v0-E
2175