Fujitsu FR81S Benutzerhandbuch
APPENDIX
B. List of Interrupt Vector
FUJITSU SEMICONDUCTOR LIMITED
APPENDIX
FUJITSU SEMICONDUCTOR CONFIDENTIAL
69
(*1) The status of the multi-function serial interface does not support the DMA transfer by the I
2
C reception.
(*2) The reload timer ch.4 to ch.7 does not support the DMA transfer by the interrupt.
(*3) The PPG ch.24 to ch.47 does not support the DMA transfer by the interrupt.
(*4) The clock calibration unit does not support the DMA transfer by the interrupt.
(*5) It does not support the DMA transfer by the interrupt because of the RAM ECC bit error.
(*6) The 32-bit free-run timer ch.3 to ch.5 does not support the DMA transfer by the interrupt.
(*7) There is no resource corresponding to interrupt level.
(*8) It does not support the DMA transfer by the external low-voltage detection interrupt.
MB91520 Series
MN705-00010-1v0-E
2279