Fujitsu FR81S Benutzerhandbuch
CHAPTER 7: RESET
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER :
RESET
FUJITSU SEMICONDUCTOR CONFIDENTIAL
9
ERST
RSTX pin reset detection, illegal standby mode
transition detection, clock supervisor reset or simultaneous
assert of RSTX and NMIX external pins
0
Undetected
1
Detected
This bit will be cleared when it is read out.
[bit5] WDG1 (WatchDoG reset 1) : Watchdog Reset 1
This bit indicates a reset from the watchdog timer 1.
In case of a reset time out due to this reset factor, IRRST along with this bit will be "1".
WDG1
Watchdog timer 1 reset
0
Undetected
1
Detected
This bit will be cleared when it is read out.
The CPUAR register also has a flag that indicates a reset factor generation by the watchdog reset 1. The bit
will not be cleared when the CPUAR register is read.
[bit4] WDG0 (WatchDoG reset 0) : Watchdog Reset 0
This bit indicates a reset from the watchdog timer 0.
In case of a reset time out due to this reset factor, IRRST along with this bit will be "1".
WDG0
Watchdog timer 0 reset
0
Undetected
1
Detected
This bit will be cleared when it is read out.
[bit1] SCRT (Flash SeCuRiTy violation) : Flash security violation reset
This bit indicates that a flash memory security violation reset has occurred.
In case of a reset time out due to this reset factor, IRRST along with this bit will be "1".
SCRT
Flash security violation reset
0
Undetected
1
Detected
This bit will be cleared when it is read out.
[bit0] SRST (Software ReSeT) : Software reset
This bit indicates a reset by writing "1" to the RSTCR:SRST bit.
In case of a reset time out due to this reset factor, IRRST along with this bit will be "1".
SRST
Software reset
0
Undetected
1
Detected
This bit will be cleared when it is read out.
MB91520 Series
MN705-00010-1v0-E
262