Fujitsu FR81S Benutzerhandbuch
CHAPTER 8: DMA CONTROLLER (DMAC)
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : DMA CONTROLLER (DMAC)
FUJITSU SEMICONDUCTOR CONFIDENTIAL
17
4.3. DMA Channel Status Register 0 to 15 : DCSR0 to 15:
(DMA Channel Status Register 0 to 15)
This section explains the bit configuration for DMA channel status register 0 to 15 .
These registers are 16-bit registers to indicate the status for each DMAC channel, which exist independently
for each channel. These registers must be accessed as a 16-bit data.
DCSR0 to 15: Address BASE + 0004
H
(Access: Half-word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
CA
Reserved
Initial value
0
0
0
0
0
0
0
0
Attribute R,WX R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R0,W0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
AC
SP
NC
Initial value
0
0
0
0
0
0
0
0
Attribute R0,W0 R0,W0 R0,W0 R0,W0 R0,W0
R,W
R,W
R,W
[bit15] CA (Channel Active) : Channel active
This bit indicates the operation of the channels. Writing "1" to the corresponding DCCRn:CE bit for the
channel makes it in the operating state. Completing transfers for as many times as set transfer count or
writing "0" to DCCRn:CE makes the operation stop.
Writing this bit is ignored.
CA
Channel operating state
0
Stop state (initial value)
1
Channel operating
[bit14 to bit3] Reserved
Always write "0" to these bits. The read value is "0".
[bit2] AC (Abnormal Completion) : Abnormal completion state
This bit indicates that a prohibited value has been set to the DMA channel control register (DCCR). The
items not allowed to set to registers are listed below.
⋅
Transfer mode
: DCCRn:TM = 10
B
⋅
Transfer source address count
: DCCRn:SAC = 10
B
⋅
Transfer destination address count
: DCCRn:DAC = 10
B
⋅
Transfer size
: DCCRn:TS = 11
B
⋅
Demand transfer mode by software request
: DCCRn:RS = 00
B
and DCCRn:TM = 11
B
MB91520 Series
MN705-00010-1v0-E
316