Fujitsu FR81S Benutzerhandbuch
CHAPTER 19: BASE TIMER
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: BASE TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
47
5.4. 16/32-bit Reload Timer Operation
This section explains the 16/32-bit reload timer operation.
This section explains the operation performed when the base timer included in this series is used as the
16/32-bit reload timer. An example is also given to set various operation conditions.
Figure 5-3 Block Diagram (16-bit Reload Timer Operation)
BTxPCSR
16-bit mode
T32=0
CKS
EGS
2
3
2
0
2
7
2
8
STRG
CTEN
CTEN
MDSE
16
BTxTMR
T32
OSEL
UDIE
TGIE
IRQ0
IRQ1
Edge
detection
BTxPCSR : Base timer x cycle setting register (BTxPCSR)
BTxTMR : Base timer x timer register (BTxTMR)
External activation
edge (TGIN signal)
Output waveform
(TOUT signal)
Invert control
Toggle
generation
Division
circuit
Edge
detection
Peripheral clock
Load
Count clock
External clock
(ECK signal)
Down counter
Underflow
Count
enabled
Count
enabled
Underflow
Trigger
Trigger
Timer enabled
generation
(PCLK)
interrupt request
interrupt request
Interrupt
source
MB91520 Series
MN705-00010-1v0-E
680