Freescale Semiconductor MC68HC08KH12 Benutzerhandbuch

Advance Information

MC68HC(7)08KH12

 — 

Rev. 1.1

66

Freescale Semiconductor

When the power-on reset module generates a reset, the clocks to the 
CPU and peripherals are inactive and held in an inactive phase until after 
the 4096 CGMXCLK cycle POR timeout has completed. The RST pin is 
driven low by the SIM during this entire period. The IBUS clocks start 
upon completion of the timeout.

Upon exit from stop mode by an interrupt, break, or reset, the SIM allows 
CGMXCLK to clock the SIM counter. The CPU and peripheral clocks do 
not become active until after the stop delay timeout. This timeout is 
selectable as 4096 or 32 CGMXCLK cycles. 

In wait mode, the CPU clocks are inactive. The SIM also produces two 
sets of clocks for other modules. Refer to the wait mode subsection of 
each module to see if the module is active or inactive in wait mode. 
Some modules can be programmed to be active in wait mode.

The MCU has these reset sources:

•

Power-on reset module (POR)

•

External reset pin (RST)

•

Computer operating properly module (COP)

•

Illegal opcode

•

Illegal address

•

Universal Serial Bus module (USB)

All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in 
monitor mode) and assert the internal reset signal (IRST). IRST causes 
all registers to be returned to their default values and all modules to be 
returned to their reset states.