Emerson 752I Benutzerhandbuch
4-1
Section 4
Processor
The Katana
752i processor complex consists of a processor and a system controller/PCI
bridge device (see Chapter ) with associated memory and input/output interfaces. The pro-
cessor complex supports soldered and socketed user Flash memory, DDR SDRAM, an EIA-
232 serial console port, and three 10/100/1000BaseT Ethernet ports.
cessor complex supports soldered and socketed user Flash memory, DDR SDRAM, an EIA-
232 serial console port, and three 10/100/1000BaseT Ethernet ports.
PROCESSOR OVERVIEW
This chapter provides an overview of the processor logic on the Katana
752i. It includes
information on the CPU, exception handling, and cache memory. The Katana
752i utilizes
the IBM PowerPC
™
750GL microprocessor. For more detailed information, please refer to
the following IBM document: PowerPC
™
Microprocessor Family: The Bus Interface for 32-Bit
Microprocessors.
Features
The following table outlines some of the key features for the 750GL CPU.
Table 4-1:
752i CPU Features
The following block diagram provides an overview of the IBM 750GL architecture.
Category:
750GL Key Features:
Instruction Set
32-bit
CPU Speed (internal)
Up to 1GHz
Data Bus
64-bit
Address Bus
32-bit
Four stage pipeline control
Fetch, dispatch/decode, execute,
complete/write back
complete/write back
Cache (L1)
32KB Instruction, 32KB Data, 8-way set
associative
associative
Cache (L2)
1MB, 4-way set associative, ECC checking
Execution Units
Branch Processing, Dispatch, Decode,
Load/Store, Fixed-point, Floating-point,
System
Load/Store, Fixed-point, Floating-point,
System
Dual issue superscalar
control
control
Maximum of two instructions completed plus
one branch folded per cycle
one branch folded per cycle
Voltages
Internal, 1.5V; input/output, 2.5V