AMD LX 900@1.5W Benutzerhandbuch
AMD Geode™ LX Processors Data Book
211
GeodeLink™ Memory Controller
33234H
Features
• Supports up to 400 MT/S (million transfers per second)
DDR SDRAMs
• Supports 64-bit data interface
• Supports unbuffered DIMMs and SODIMMs
• Can maintain up to 16 open banks at a time
• Can support up to three outstanding requests at a time
• Arbiter reorders requests from different sources to opti-
mize data bus utilization
• Single and burst data phase optimization
• Programmable modes of high and low order address
interleaving
• Queues up to eight refreshes
• Supports low power mode
• Highly configurable to obtain best performance for
installed DRAM
6.1.1
Functional Hardware
6.1.1.1
Address Translation
The GLMC module supports two address translations
depending on the method used to interleave pages. The
hardware supports High Order Interleaving (HOI) or Low
Order Interleaving (LOI). Select the interleaving mode used
by programming the HOI_LOI bit of the MC_CF8F_DATA
register (MSR 20000019h[33]. See Section 6.2.2.10 "Tim-
ing and Mode Program (MC_CF8F_DATA)" on page 229 for
bit description.
depending on the method used to interleave pages. The
hardware supports High Order Interleaving (HOI) or Low
Order Interleaving (LOI). Select the interleaving mode used
by programming the HOI_LOI bit of the MC_CF8F_DATA
register (MSR 20000019h[33]. See Section 6.2.2.10 "Tim-
ing and Mode Program (MC_CF8F_DATA)" on page 229 for
bit description.
High Order Interleaving
High Order Interleaving (HOI) uses the most significant
address bits to select which bank the page is located in.
Figure 6-3 shows an example of how the Geode LX pro-
cessor’s internal physical addresses are connected to the
memory interface address lines.
address bits to select which bank the page is located in.
Figure 6-3 shows an example of how the Geode LX pro-
cessor’s internal physical addresses are connected to the
memory interface address lines.
This interleaving scheme works with any mixture of DIMM
types. However, it spreads the pages over wide address
ranges. For example, assume a 64 MB memory subsystem
with two 32 MB DIMMs installed. Each DIMM has a single
module bank, and each module bank contains four compo-
nent banks. This gives a total of eight component banks in
this memory configuration. Each page in a component
bank is separated from the next component bank page by
8 MB. See Figure 6-4.
types. However, it spreads the pages over wide address
ranges. For example, assume a 64 MB memory subsystem
with two 32 MB DIMMs installed. Each DIMM has a single
module bank, and each module bank contains four compo-
nent banks. This gives a total of eight component banks in
this memory configuration. Each page in a component
bank is separated from the next component bank page by
8 MB. See Figure 6-4.
Figure 6-3. HOI Addressing Example
Figure 6-4. HOI Example
aaaaaaaaaaaaaaaaaaaaaaaaaa
22222222211111111110000000
87654321098765432109876543
22222222211111111110000000
87654321098765432109876543
BA[1:0]
MB[1]
RA[9:0]
CA[7:0]
CA[7:0]
MB[0]
RA[12:10]
Internal
Physical
Address
Physical
Address
CA are the CAS addresses on MA[7:0]
RA are the RAS addresses on MA[12:0]
Module Bank
Component Banks
Bank
3
Page 0
DIMM0
DIMM1
00000000h
00800000h
01000000h
01800000h
24M
Bank
2
Page 0 16M
Bank
1
Page 0 8M
Bank
0
Page 0 0M
Module Bank
Component Banks
Bank
3
Page 0
02000000h
02800000h
03000000h
03800000h
56M
Bank
2
Page 0 48M
Bank
1
Page 0 40M
Bank
0
Page 0 32M