AMD LX 900@1.5W Benutzerhandbuch
46
AMD Geode™ LX Processors Data Book
GeodeLink™ Interface Unit
33234H
4.1.1
Port Address
Each GLIU has seven channels with Channel 0 being the
GLIU itself and therefore not considered a physical port.
Figure 4-1 illustrates the GeodeLink architecture in a
AMD Geode LX processor, showing how the modules are
connected to the two GLIUs. GLIU0 has five channels con-
nected, and GLIU1 has six channels connected. To get
MSR address/data across the PCI bus, the GLPCI converts
the MSR address into PCI cycles and back again.
GLIU itself and therefore not considered a physical port.
Figure 4-1 illustrates the GeodeLink architecture in a
AMD Geode LX processor, showing how the modules are
connected to the two GLIUs. GLIU0 has five channels con-
nected, and GLIU1 has six channels connected. To get
MSR address/data across the PCI bus, the GLPCI converts
the MSR address into PCI cycles and back again.
An MSR address is parsed into two fields, the port address
(18 bits) and the index (14 bits). The port address is further
parsed into six 3-bit channel address fields. Each 3-bit field
represents, from the perspective of the source module, the
GLIU channels that are used to get to the destination mod-
ule, starting from the closest GLIU to the source (left most
3-bit field) to the farthest GLIU (right most 3-bit field).
(18 bits) and the index (14 bits). The port address is further
parsed into six 3-bit channel address fields. Each 3-bit field
represents, from the perspective of the source module, the
GLIU channels that are used to get to the destination mod-
ule, starting from the closest GLIU to the source (left most
3-bit field) to the farthest GLIU (right most 3-bit field).
In aN AMD Geode LX processor/CS5536 system, the com-
panion device is connected to the processor via the PCI
bus. The internal architecture of the companion device
uses the same GeodeLink architecture with one GLIU
being in that device. Hence, in a AMD Geode LX proces-
sor/CS5536 system there are a total of three GLIUs: two in
the processor and one in the companion device. Therefore
at most, only the two left most 3-bit fields of the base
address field should be needed to access any module in
the system. There are exceptions that require more; see
Section 4.1.2 "Port Addressing Exceptions" on page 47.
For the CPU Core to access MSR Index 300h in the
GeodeLink Control Processor (GLCP) module, the address
is 010_011_000_000_000_000b (six channel fields of the
port address) + 300h (Index), or 4C000300h. The 010b
points to Channel 2 of GLIU0, which is the channel con-
nected to GLIU1. The 011b points to the GLIU1 Channel 3,
which is the channel to the GLCP module. From this point
on, the port address is abbreviated by noting each channel
address followed by a dot. From the above example, this is
represented by 2.3.0.0.0.0. It is important to repeat here
that the port address is derived from the perspective of the
source module.
panion device is connected to the processor via the PCI
bus. The internal architecture of the companion device
uses the same GeodeLink architecture with one GLIU
being in that device. Hence, in a AMD Geode LX proces-
sor/CS5536 system there are a total of three GLIUs: two in
the processor and one in the companion device. Therefore
at most, only the two left most 3-bit fields of the base
address field should be needed to access any module in
the system. There are exceptions that require more; see
Section 4.1.2 "Port Addressing Exceptions" on page 47.
For the CPU Core to access MSR Index 300h in the
GeodeLink Control Processor (GLCP) module, the address
is 010_011_000_000_000_000b (six channel fields of the
port address) + 300h (Index), or 4C000300h. The 010b
points to Channel 2 of GLIU0, which is the channel con-
nected to GLIU1. The 011b points to the GLIU1 Channel 3,
which is the channel to the GLCP module. From this point
on, the port address is abbreviated by noting each channel
address followed by a dot. From the above example, this is
represented by 2.3.0.0.0.0. It is important to repeat here
that the port address is derived from the perspective of the
source module.
For a module to access an MSR within itself, the port
address is zero.
address is zero.
Figure 4-1. GeodeLink™ Architecture
GLMC
CPU Core
DC
GLIU1
7
6
1
3
4
5
2
0
GLIU0
GP
GLIU0
1
2
3
5
4
6
7
0
GLIU1
GLPCI
GLPCI
PCI Bus
VP
GLCP
VIP
Not Used
Not Used
SB
Not Used
(AES)